Hitachi, Ltd.

Nippon Telegraph and Telephone Corporation

Hitachi Vlsi Engineering Corp.

Junichirou Yanagi

Takahiko Kozaki

Kaoru Aoki

Akihiko Takase

Yutaka Ito

Kiyoshi Aiki

Shinobu Gohara

Yoshihiro Ashi

Masataka Takano

Setsuo Takahashi

Tetsushi Nakano

Miho Iino

Yukio Nakano

Masahiro Takatori

Noboru Endo

Ryoji Takeyari

Takashi Mori

Shiro Tanabe

Yusuke Mishina

Morihito Miyagi

Ken'ichi Sakamoto

Toshiya Oouchi

Takashi Nakashima

Katuyoshi Tanaka

An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

ATM cell switching system

An ATM handler that sets a switchover indication to a control register according to a system switchover order from a controller such that a switchover indication is supplied to a selector and line interfaces according to an output signal from the register. The setting of a switchover indication synchronize a switchover of an operation to count user cells between the line interfaces of the active and standby systems with a switchover of a stream of input cells to an ATM switch by a selector. A protection period is provided to allow a time after the system switchover according to a transmission delay lag. The line interface related to a delayed phase assigns a bit for stopping counting to cells input during the protection period so that the counting operation is conducted for the cells other than those assigned with the bit for stopping counting. As a result, duplicate of counting cells is prevented and the number of user cells are accurately counted.

Asynchronous transmission mode (ATM) handler

Apparatus for executing the connection admission control for PVC and SVC efficiently in an ATM network system which includes a network management equipment and a network equipment. The control function of the network management equipment executes resource allocation to PVC and SVC and notifies the network equipment of resource management information for SVC. For a request of PVC setup, the control function of the network management equipment executes the connection admission control for PVC and notifies the network equipment of the admission result. For a request of SVC setup, the network equipment executes the connection admission control for SVC. Communication overhead is reduced since it is not necessary to inquire the network equipment about connection admission from the network management equipment during PVC setup. Furthermore, the network equipment can count call blocking of SVC.

ATM network system and connection admission control method

An ATM communication system including a plurality of communication nodes connected in a loop form by buses, buffers disposed in each communication node, a synchronizing pulse generation circuit for conducting cell demultiplexing of all communication nodes at the same timing, storage devices disposed in each communication node to store mounting position information of the communication node and slot generator position information, and a circuit used by each communication node to automatically transmit and receive cells on the basis of position information described above.

ATM communication system

A looped bus system includes several nodes connected by unidirectional buses having opposite directions of signal transmission. The head of bus function for each bus is located at a node different from the head of bus function for the other bus. The head of bus function for each bus is located at the same node as the termination of bus function for the other bus. As a result, the buses can be reconfigured and nodes can be added freely by the use of a bus portion that is unused in the looped bus under normal condition.

Looped bus system for connecting plural nodes or plural circuit cards

Distributed LANs are connected to a wide area network through terminal adapters, which are interconnected by virtual circuits to form a logical bus network. Each terminal adapter copies cells received through the virtual circuit that is allocated for multicasting, and transfers the copied cells to the adjacent terminal adapters via preset virtual circuits. The terminal adapters assemble a part or all of the transmitted message from the received cells and, according to the contents of the assembled message, transfer the copies of the cells to the adjacent terminal adapters through predetermined virtual circuits.

Multicast communications method

ATM communication system having a physical loop form with logical start

A looped bus system includes several nodes connected by unidirectional buses having opposite directions of signal transmission. The head of bus function for each bus is located at a node different from the head of bus function for the other bus. The head of bus function for each bus is located at the same node as the termination of bus function for the other bus; As a result, the buses can be reconfigured and nodes can be added freely by the use of a bus portion that is unused in the looped bus under normal condition.

An ATM switching system which includes an input interface which is provided every incoming line and serves to convert header information of each input cell into internal routing information, a shared buffer memory and a cell writing control unit which forms normal cell list structures, which are prepared in correspondence to outgoing lines and in which a plurality of normal cells are chained together with their next addresses, and a broadcast cell list structure, in which a plurality of broadcast cells are chained together with their next addresses, in the shared buffer memory, and serves to add successively the input cells to ones of the list structures, which are selected in correspondence to respective internal routing information. The invention also includes a cell reading control unit which serves to fetch selectively the cell from the list structures formed in the shared buffer memory to distribute the cell thus fetched to the associated outgoing lines. The cell reading control unit includes a broadcast destination table for 'storing broadcast destination specifying information for specifying the outgoing lines, through which the broadcast cell is to be output, using a bit pattern, in correspondence to the internal routing information of the broadcast cell'.

Shared buffer memory type ATM communication system and method with a

ATM switch1ng system connectable to I/O links having different

Growing community of inventors

Kodaira, Japan

Junichirou Yanagi