Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Junichi Yano

Masanori Tsutsumi

Hidetoshi Nishimura

Tetsurou Toubou

Nana Okamoto

Emi Mizushino

Junya Yamamoto

Genichiro Inoue

Fumihiro Kimura

Katsuyuki Imamura

Hisato Yoshida

Junichi Mori

Kimihiko Aiba

Masayuki Matsuda

A semiconductor integrated circuit includes a first transistor which is formed of a first gate extending in a first direction and a first diffusion region and which is capable of being active, a second transistor which is formed of a second gate extending in the first direction and a second diffusion region and which is arranged adjacent to the first transistor in a second direction intersected at a right angle with the first direction, and a third gate which extends in the first direction and which is arranged adjacent in the second direction to the first transistor on an opposite side to the second transistor. A space between the first gate and the second gate is larger than a space between the first gate and the third gate.

Semiconductor integrated circuit, standard cell, standard cell library, semiconductor integrated circuit designing method, and semiconductor integrated circuit designing equipment

In the present invention, a decoupling capacitance circuit, a first output terminal and a second output terminal are provided. The decoupling capacitance circuit comprises a TDDB control circuit consisting of a first Tr and a second Tr, and a third Tr. Conductivity types of the first and second Trs are different from each other. A source of the first Tr is connected to a first power supply wiring, and a drain of the first Tr is connected to a gate of the second Tr. A source of the second Tr is connected to a second power supply wiring, and a drain of the second Tr is connected to a gate of the first Tr. The third and first Trs have the same conductivity type. A source and a drain of the third Tr are connected to the first power supply wiring, and a gate of the third Tr is connected to the drain of the second Tr. The first output terminal is connected to the drain of the first Tr, and the second output terminal is connected to the drain of the second Tr.

Semiconductor integrated circuit and method of designing semiconductor integrated circuit

In a standard cell, at least one of transistors on either side of a transistor having gate length different from that of the other transistors are set to be always in the OFF state. This prevents influence to the operation of the standard cell even with variation in final gate dimension, suppressing variation in characteristics of the standard cell.

Standard cell, standard cell library, and semiconductor integrated circuit with suppressed variation in characteristics

VSSis provided to a gate portionand VDDis provided to a source portionand a drain portionof a MOS transistor which constitutes a decoupling capacitor, and a potential NWVDDdifferent from that provided to the source portionand the drain portionis provided to a substrate portion. If NWVDDis set higher than VDD, a depletion layeris spread, so that a leakage current can be reduced instead of reducing a capacitance of the decoupling capacitor. In addition, if NWVDDis set lower than VDDso as not to cause latchup, the depletion layeris reduced, so that the capacitance of the decoupling capacitor can be increased. By changing the potential NWVDDprovided to the substrate portion, a capacitance value and a leakage current value of the decoupling capacitor can be controlled. Thereby making it possible to achieve a decoupling capacitor capable of controlling the capacitance value and the leakage current value and also having excellent response characteristics.

Decoupling capacitors and semiconductor integrated circuit

By forming adjacent wiringadjacent to signal wiringand using a control circuitcomprising a 2-input NANDcircuit or the like to input a signal Scorresponding to a signal Sin the signal wiringto the adjacent wiringit is made possible to change the delay of the signal Sin the signal wiringin several picoseconds, by using crosstalk with the signal Sin the signal wiringThe inventive delay control circuit device can be provided by simply adding adjacent wiringand a control circuitto signal wiring. This implements a delay control circuit device for semiconductor integrated circuits that is capable of controlling a signal delay in several picoseconds without increasing the circuit scale.

Delay control circuit device, and a semiconductor integrated circuit device and a delay control method using said delay control circuit device

In a dynamic circuit, when only between a precharge node and an intermediate node through a plurality of logical-operating MOS transistors is conducted, the potential of the precharge node approximately drops to High*{C/(C+C)} from High, where Crepresents the capacitance of the precharge node and Crepresents the capacitance of the intermediate node. Thereafter, with the charge from a power supply, the precharge node returns to High. At this charge sharing time, the amount of charge supply from the power supply is adjusted to suppress voltage drop of the precharge node, thereby reducing noise.

Dynamic circuit

A semiconductor integrated circuits can send and receive signals to and form a configuration memory. The semiconductor integrated circuits is provided therein wiht an instruction memory, an instruction storage portion that stores reserved instructions as F instructions, and stores the substantially equivalent processing contents to the F instructions as substitute instructions for processing by the CPU, a pre-fetch portion, a history storage portion, a diagnosing portion for diagnosing the types of instructions, a reprogramming control portion for reprogramming the instructions, a CPU, an FPGA, a configuration data memory, a built-in memory, and a configuration data tag. When the configuration data of the F instruction does not exist in the FPGA, the substantially equivalent processing by FPGA is executed by the CPU by making use of the substitute instructions.

Integrated circuit with CPU and FPGA for reserved instructions execution with configuration diagnosis

A standard cell for a plurality of power supplies comprises a first power line and a second power line electrically isolated from the first power line. An N well is arranged in spaced relation with the whole peripheral boundaries of the standard cell. In the case where the standard cells are arranged adjacently to each other in the direction along the power lines or in the direction orthogonal thereto, the N well in the standard cell for a plurality of power supplies is isolated from the N wells of the adjacent standard cells in the direction along the power lines or in the direction orthogonal thereto, as the case may be.

Standard cell for plural power supplies and related technologies

The semiconductor integrated circuit of this invention includes a first transistor for setting a first node at a first logic level in accordance with a clock signal; an input circuit for setting the first node at a second logic level in accordance with an input signal; a second transistor for setting a second node at the first logic level when the first node is at the first logic level; a resistor device connected between the first node and the second node; a first driving transistor for receiving, as an input, potential of the second node and controlling whether or not an output node is set at the first logic level; and a second driving transistor for receiving, as an input, a signal at a logic level identical to the logic level of the first node and controlling whether or not the output node is set at the second logic level.

Growing community of inventors

Osaka, Japan

Junichi Yano