Nec Corporation

Matsushita Electric Industrial Co., Ltd.

Dai Nippon Printing Co., Ltd.

Matsushita Electric Works, Ltd.

Hitachi, Ltd.

Stanley Electric Co., Ltd

Ihi Corporation

Shin Meiwa Industry Co., Ltd.

Fuji Photo Co., Ltd.

Panasonic Electric Works, Ltd.

Junichi Yamada

Tadakazu Narikawa

Nobutaka Kato

Hirofumi Takemasa

Eiichiro Naito

Hiroyuki Maeno

Taro Mochida

Yoshiyuki Miyake

Joseph J Nukazawa

Yukio Hirano

Takashi Horiguchi

Kunio Funatsu

Tohru Nishiyama

Sakpanom Srisawas

Kunihiro Tsubosaki

Hideki Sato

Hiroki Koike

Yasuo Sato

Hirotaka Takahashi

Yasushi Tomita

Masaaki Aoki

Akira Arai

Tsutomu Kawamura

Daisuke Hisajima

Masahiro Matsubara

Yasushi Harada

Nobuhisa Kobayashi

Jiro Kobayashi

Kazuya Matsuo

Yo Shimazaki

Taketoshi Mochizuki

Mituo Kudo

Kenichi Kuwabara

Noriyuki Miyake

Genichiro Nishi

Keizi Shono

Masaichi Ohmori

Motohiro Aoki

A battery control apparatus includes a reduced electricity cost analysis unit that obtains a discharge electric power cost at a discharge time and a charge electric power cost at a charge time of a battery, based on a basic cost and a unit cost of an electricity bill, and obtains a reduced electricity cost in which the charge electric power cost is subtracted from the discharge electric power cost for every discharge depth of the battery; an introduction cost analysis unit that calculates an introduction cost of the battery for every discharge depth of the battery; and a charge and discharge depth optimization unit that obtains a difference of the reduced electricity cost and the introduction cost for every discharge depth of the battery, and determines a charge and discharge depth of the battery based on the difference. The discharge of the battery is performed at the determined charge and discharge depth.

Battery control apparatus

Provided is a cutting device including a machining table configured to float a workpiece having a plate shape, a laser radiation unit configured to radiate a laser beam onto the workpiece, a coolant injection unit configured to inject a coolant onto the workpiece, and a moving device configured to relatively move the workpiece with respect to the laser radiation unit and the coolant injection unit in a preset direction. In the cutting device, a scattering member configured to receive injection of the coolant from the coolant injection unit and scatter the coolant is installed at the machining table in front of the workpiece in a moving direction in which the workpiece relatively moves.

Cutting device

A lamp including a plurality of light emitting devices and heat sinks can be configured to dissipate heat generated by the plurality of light emitting devices. The heat sinks can be branched into a generally Y-shaped configuration as viewed in a section that includes a primary optical axis of the vehicle lamp. One of the light emitting devices is connected to one of the branched parts of the heat sinks. Another light emitting device is connected to the other branched part of the heat sinks.

Lamp and method of manufacturing same

Lamp with heat sink configuration and method of manufacturing same

Electric massaging chair

A system for managing energy consumption has a data storage module, a calculation module and an operation planning module. The data storage module stores an operational past record of a unit belonging to a facility to be managed by the system. The calculation module calculates wasteful energy consumption for the unit based on the operational past record stored in the data storage module. The operation planning module generates an operational plan for the unit belonging to the facility based on the wasteful energy consumption calculated by the calculation module.

Method, system and computer program for managing energy consumption

Exercise device

In a semiconductor memory incorporating therein a circuit for relieving a defective memory cell, a memory cell array constituted of a number of main memory cells MCto MCis added with one column of redundant memory cells MCto MCand one word line of substitution information storing memory cells MCRAto MCRA. In only a first cycle after the power supply is turned on, the substitution information DRto DRj is read out from the substitution information storing memory cells by use of a writing/reading circuit associated with the main memory cells, and is transferred to and held in a control circuit. In a second and succeeding cycles, the control circuit generates Y selection circuit control signals CSto CSj on the basis of the substitution information held in the control circuit, and a Y selection circuit is controlled by the control signals CSto CSj so as to selectively connect the columns other than a defective column to an input/output line. Thus, a chip area overhead attributable to the installation of the defective memory cell relief circuit is minimized. In addition, an address comparing circuit for a defective memory cell substitution is no longer necessary, and an access time overhead attributable to the address substitution operation does not occur.

Semiconductor memory having a defective memory cell relieving circuit

In a semiconductor memory incorporating therein a circuit for relieving a defective memory cell, a memory cell array constituted of a number of main memory cells MC00 to MCij is added with one column of redundant memory cells MC0j&plus;1 to MCij&plus;1 and one word line of substitution information storing memory cells MCRA0 to MCRAj&plus;1. In only a first cycle after the power supply is turned on, the substitution information DR0 to DRj is read out from the substitution information storing memory cells by use of a writing/reading circuit associated with the main memory cells, and is transferred to and held in a control circuit. In a second and succeeding cycles, the control circuit generates Y selection circuit control signals CS0 to CSj on the basis of the substitution information held in the control circuit, and a Y selection circuit is controlled by the control signals CS to CSj so as to selectively connect the columns other than a defective column to an input/output line. Thus, a chip area overhead attributable to the installation of the defective memory cell relief circuit is minimized. In addition, an address comparing circuit for a defective memory cell substitution is no longer necessary, and an access time overhead attributable to the address substitution operation does not occur.

A ferroelectric memory device has a ferroelectric capacitor comprising a ferroelectric thin film and a first capacitive electrode and a second capacitive electrode which sandwich the ferroelectric thin film therebetween. The ferroelectric memory device is operable in a wide range of allowable power supply voltages such that it can operate at a low power supply voltage. The ferroelectric thin film is formed such that a coercive voltage thereof is smaller than a reduced voltage applied between the first capacitive electrode and the second capacitive electrode and generated by reducing an external power supply voltage supplied in a predetermined voltage range.

Ferroelectric memory device

A member for mounting of semiconductor is comprised of a substrate, a concave portions for electrode and a concave portion for wire formed on one surface of the substrate, electrode terminals formed in the concave portions for electrode, and a wire formed in the concave portion for wire, in which the concave portions for electrode terminals are formed deeper than the concave portions for wire. In the pattern-forming process, resist pattern having an opening for wire and openings for electrode in which a width of the openings for electrode is larger than a width of the portion for wire is formed on one surface of a substrate. In the etching process, a substrate is half-cut by etching a substrate through the resist pattern as a mask so that concave portions for electrode and a opening for wire are formed on the surface of the substrate. In the plating process, the substrate is plated through the same resist pattern as a mask to form electrode terminals in the concave portions for electrode and a wire in the concave portion for wire. In the peeling process, the resist pattern is removed off from the substrate, so that a member for mounting of semiconductor can be obtained.

Member for mounting of semiconductor

There is provided a highly reliable non-volatile ferroelectric memory device in which the permitted number of read/write operation cycles is increased. The device comprises a step-down power supply circuit which generates a supply voltage VINT which is lower than a supply voltage VDD fed from the outside but not less than a coercive voltage of the ferroelectrics for the purpose of improving the resistance to fatigue of and imprinting to the ferroelectrics. Since the characteristics of the ferroelectrics deteriorate more due to fatigue and imprinting as the voltage applied to the ferroelectrics increases, a supply voltage for sense amplifiers and voltage supply circuits are selected to be VINT so that VINT is applied to the ferroelectric capacitors, while a supply voltage for other peripheral circuits is selected to be VDD. With this structure, the reliability of the device with respect to its read/write operations can significantly be improved as compared to the conventional ferroelectric memory devices by minimizing the effect that the signal voltage is reduced and by increasing the permitted number of operation cycles.

Ferroelectric memory device having an internal supply voltage, which is lower than the external supply voltage, supplied to the memory cells

Growing community of inventors

Tokyo, Japan

Junichi Yamada