Kabushiki Kaisha Toshiba

Junichi Tsujimoto

Hideki Takeuchi

Mototaka Kuribayashi

Kentaro Kuroiwa

Yasuhiro Tonooka

In the timing analysis method, connection information is compared to circuit patterns that have been stored in a memory in advance after reading the connection information of an electrical circuit, a connection information supplement process to supplement vertically circuit connection information regarding the matched circuit pattern for the stored connection information is performed when the connection information is matched with one of the registered circuit patterns, and a timing analysis of the connection information that has been supplemented by the connection information supplement process is executed.

Pattern matching method, timing analysis method and timing analysis device

The present invention provide a system and a method for analyzing the static timing for LSIs which involves rather a small number of false paths contained in output results and also which reduces the processing time required. A static-timing analysis technique according to the present invention comprises a net-list input step S110 which inputs per-transistor basis connection information, to construct an internal data structure for analysis; an expected-value check step S120 which checks, against the above-mentioned internal data structure, each node on whether its expected values may be a high-impedance state; a signal-flow direction narrow-down step S130 which narrows down the directions in which the transistor signal may flow, based on the obtained expected values; a division step S140 which divides a sequential circuit into units consisting of only combinational sub-circuits; a path search step S150 which searches paths for each of thus divided units; and an output step S170 which outputs the obtained results.

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Tokyo, Japan

Junichi Tsujimoto