Hitachi, Ltd.

Hitachi Engineering Co., Ltd.

Hitachi Microcomputer Engineering, Ltd.

Junichi Tatezaki

Shigeki Morinaga

Hisashi Kaziwara

Takeshi Asai

Mitsuru Watabe

Norio Nakagawa

Hiroyuki Kida

Kazuhiko Iwasaki

Yugo Kashiwagi

Tetsuaki Nakamikawa

Tsuneo Funabashi

Masahisa Narita

Shunpei Kawasaki

Takanori Shimura

Noboru Yamaguchi

Atsushi Hasegawa

Ikuya Kawasaki

Makoto Hanawa

Takuichiro Nakazawa

Yasuhiro Sagesaka

Hideo Wada

Mamoru Ohba

Yoshifumi Kawamura

Atsushi Ogane

Isao Kodama

A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.

Multiplication, division and square root extraction apparatus

System for obtaining strict solution in accordance with accuracy of

A base station (5) comprises a base transmitter (6) for transmitting information optically to a plurality of portable stations (1 to 4) at such a predetermined time interval as is designated by portable station designating information. Each of the portable stations (1 to 4) comprises a potable transmitter (7) for transmitting information optically to the base station (5) in response to the transmission, which is designated by the portable station designating information coming from said base station (5), and within the range of the aforementioned time interval immediately after said transmission. Transmissions (ACK1 to ACK4) from the mating portable stations to the base station are individually inserted between the interval periods of the transmissions (REQ1 to REQ4) from the base station (5) to the portable stations (1 to 4) so that the single base station performs optical communications with the plurality of portable stations in a half-duplex time sharing manner.

Information transmitting/processing system

The interface portion of a coprocessor is provided with a FIFO (First-In First-Out) buffer and means for accepting instructions in succession. Pipeline control of the instructions becomes possible in this way, and protocol means associated with a microprocessor is also provided.

Coprocessor executing pipeline control for executing protocols and

A microcomputer system has a microprocessor and a number of independent coprocessors for executing individual instructions according to instruction data sent from the microprocessor. An address bus and a data bus interconnect the coprocessors with the microprocessor. The microprocessor sends instruction data to the coprocessors via the data bus and concurrently sends coprocessor designation data to the coprocessors via the address bus. The coprocessor designated by the designation data reads and reacts to the instruction data while the other coprocessors within the system disregard the instruction data.

System using microprocessor address lines for coprocessor selection

In a microprogram controller by pipeline control which includes a memory for storing a microprogram and a program counter for representing the address of the memory, a microprogram controller includes means for judging whether or not a branch condition of a branch microinstruction is satisfied and means for converting the microinstruction fetched from the memory to a NOP (No Operation) microinstruction from the output of the next step of the memory till the outputs after a plurality of steps by the affirmation output of the judging means. When the affirmation output is obtained from the judging means, part of the memory output is loaded into the program counter and when the negation output is obtained, a value as the sum of a current value plus 1 is loaded into the program counter.

Microprogram controller in which instruction following conditional

In an apparatus for decoding cyclic codes generated by a generator polynomial ##EQU1## (where P.sub.i (x) is a m.sub.i -order irreducible polynomial) including 0-th to l-th feedback shift registers corresponding to the terms (x.sup.c +1) and P.sub.i (x), a coincidence circuit for detecting coincidence of a predetermined number of low order bits of said 0-th to l-th feedback shift registers and all-zero conditions of a high order bits, the predetermined number being a minimum one of numbers of bits (c, m.sub.1, m.sub.2, . . . m.sub.l) of the feedback shift register, the 0-th feedback shift register having an output terminal thereof connected to an input terminal thereof, and the 1st to l-th feedback shift registers each having an output terminal thereof connected to an input terminal thereof and having exclusive OR gates inserted between stages determined by the associated simple polynomial, exclusive OR gates each receiving the output of the associated feedback shift register as one input thereto; a method for decoding the cyclic code for correcting a burst error by shifting the 0-th to l-th feedback shift registers until the coincidence circuit detects the coincidence, comprising the steps of; shifting at least one of said 0-th to l-th feedback shift registers a predetermined number of times; and simultaneously shifting the 0-th to l-th feedback shift registers after the predetermined number of shifting until the coincidence circuit detects the coincidence.

Decoding method and apparatus for cyclic codes

A data buffer is connected to the first and second processor and the first processor sends a start signal to the second processor, which responds to the start signal by reading data from a data source, such as an input/output device, and then writes the read out data into the data buffer. After conclusion of the writing operation, the second processor sends an end signal to the first processor which is admitted to start sending data stored in the buffer to a host processor after receipt of the start signal. The start signal and the end signal are provided to the second processor and the first processor respectively, after passing through a synchronizing circuit.

Data processing system with an enhanced communication control system

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Kodaira, Japan

Junichi Tatezaki