Sharp Kabushiki Kaisha Corporation

Junichi Tanimoto

Masahiro Hasegawa

Yoshinao Morikawa

Toshiji Ishii

Setsufumi Kamuro

Akira Yamaguchi

Mikiro Okada

Takaaki Hirano

Toshihisa Gotou

A semiconductor device for display control includes an input section for receiving a display information including a character code, a display position information and a character size information, a first address generating section for generating a first address group corresponding to the received character code by applying a predetermined conversion rule to the received character code and character size information, a font data storing section for outputting the font data stored in the region specified by the first address group when the first address group is given, a second address generating section for generating a second address group by utilizing the received display position information, the second address group representing a region where the font data is to be expanded, a font data expanding section for expanding and temporarily storing the font data in the region represented by the second address group, and an output section for outputting the font data to an external display driving unit.

Semiconductor device for display control

A semiconductor device formed on a semiconductor substrate; includes diffusion layers for source and drain regions formed in a surface portion of the semiconductor substrate. A gate electrode is formed on the semiconductor substrate with an intervening gate insulation film. An interlayer insulation film is formed on the gate electrode, and an interconnection layer is formed on the interlayer insulation film. The gate electrode is formed on at least a portion of the source and drain regions and on a channel region located between the source and drain regions. The gate electrode is electrically connected to the interconnection layer via a contact hole formed in the interlayer insulation film on the gate electrode.

Semiconductor device and fabrication process therefor

A semiconductor device comprises a semiconductor substrate formed with at least one well containing impurity ions of either a first conductivity type or a second conductivity type; a plurality of transistors each having a gate insulation film formed on the well, a gate electrode formed on the gate insulation film and a pair of diffusion layers formed in the well; and an outer diffusion layer of the same conductivity type as that of the well and self-aligned with each of the diffusion layers in an outer periphery thereof within the well; the outer diffusion layer having an impurity concentration sufficient to provide a desired junction withstand voltage and having substantially the same width as that of a depletion layer to be generated when an operational voltage is applied to the corresponding transistor; the impurity of the well being set for a concentration such that a threshold voltage of a parasitic transistor appearing below the gate electrode connecting adjacent transistors is higher than a power supply voltage, whereby the adjacent transistors are isolated from each other.

Method of fabricating mask ROM using junction isolation

Semiconductor device with outer diffusion layer

A delay circuit comprises first modified inverter circuits, a first compensating circuit, second modified inverter circuits and second compensating circuit. Each first modified inverter circuit is composed of a CMOS inverter and an additional NMOS transistor. The CMOS inverter has an NMOS and a PMOS transistor connected in complementary connection between a positive power supply and ground. The additional NMOS transistor controls the current from the first modified inverter circuit to the ground. The first compensating circuit is connected to the gate of each additional NMOS transistor to supply an output signal for compensating a change in characteristic of the additional NMOS transistors. Each second modified inverter circuit is composed of a CMOS inverter and an additional PMOS transistor. The additional PMOS transistor controls a current from the second modified inverter circuit to the positive power supply. The second compensating circuit is connected to the gate of each additional PMOS transistor to supply an output signal for compensating a change in characteristic of the additional PMOS transistors. The first modified inverter circuits and the second inverter circuits are connected to each other to provide an output signal from the delay circuit which is delayed relative to an input signal into the delay circuit. The delay circuit may have a constant delay time event with variations in MOS transistor characteristic (Vth) and in ambient temperature.

Constant CMOS delay circuit

A step-down circuit for power supply voltage, which converts an external power supply voltage into a first voltage that is lower than the external power supply voltage so as to apply it to an internal circuit, is provided with: a reference voltage generation circuit for generating a reference voltage from an external power supply voltage, a differential amplification circuit for releasing a difference between the reference voltage and the first voltage as a control signal, a driving circuit for controlling a driving current to be supplied to the internal circuit according to the control signal from the differential amplification circuit, a signal generation circuit for releasing a detection signal by detecting an increase of consumption current in the internal circuit, and a control means for controlling the driving circuit so as to increase the current to be supplied to the internal circuit in accordance with the detection signal from the signal generation circuit. Even if the consumption current of the internal circuit increases, this arrangement makes it possible to restrict the drop of the first voltage to be applied to the internal circuit to a minimum value.

Step-down circuit for power supply voltage capable of making a quick

A peripheral unit for a microprocessor system connected to a microprocessor comprises means for selecting whether an operation of the peripheral unit is to be halted in response to an inputted signal, and means for prohibiting the supply of a signal for activating the peripheral unit in response to the output of the selecting means. The peripheral unit, further, comprises means for canceling the operation of the prohibiting means to supply the signal for activating the peripheral unit in response to a second inputted signal. The peripheral unit and the microprocessor are constructed of CMOS transistors.

Growing community of inventors

Ikoma, Japan

Junichi Tanimoto