Oki Electric Industry Co., Ltd.

Junichi Suyama

Akihiro Hirota

Kazukiyo Fukudome

Wataru Nagai

Takayuki Tanaka

Shota Ohtsubo

Yuki Hashimoto

Shizuo Cho

Takeru Yonaga

Yasuhiro Tokunaga

Yoshihiro Murashima

Jouji Ueno

A power-source controller for reducing current consumption while a DRAM is in standby, includes a mode detection circuit inverting a disable signal having an L-level under the enable state and having an H-level under the disable state; an internal-power-source driver circuit having first and second transistors; and an internal-power-source reference circuit setting first and second driver control signals respectively to L-level and H-level when an L-level disable signal is input to turn on the first transistor and turn off the second transistor, supplying an external-power-source voltage as an internal-power-source voltage, setting the first driver control signal to H-level when an H-level disable signal is input, controlling the level of the second driver control signal to turn off the second transistor and control the first transistor, and supplying an internal power-source voltage lower than the external-power-source voltage.

DRAM power-source controller that reduces current consumption during standby

A low power consumption type dynamic random access memory (DRAM) operable with reduced current consumption responsive to an external signal, without causing occurrence of malfunction during low current consumption. An input circuit for receiving signals, a memory array for holding data, and a peripheral circuit for controlling the memory array are driven by an internal voltage supplied by two groups of internal voltage receiving circuits, while an output circuit for outputting signals is driven by an external power supply. The two groups of internal voltage receiving circuits are deactivated in response to an externally provided power supply control signal, and the output circuit is controlled so as to be in a high impedance condition with voltage of the external power supply being applied thereto.

Dynamic random access memory with low power consumption

A determining circuit comprises an input section having a P-channel type MOS transistor applied with a voltage VT set based on a reference voltage applied to a gate electrode and a voltage according to a voltage of a terminal applied to a source electrode, and an output section with a voltage level that changes according to an output from a drain electrode of a P-channel-type MOS transistor of a voltage level that changes according to a further voltage. With this configuration, the determining circuit for determining switching over to a prescribed mode can be implemented which is not influenced by fluctuations in process factors by using the voltage outputted from the output section.

Semiconductor integrated circuit

There provides a low power consumption type dynamic random access memory (DRAM) with reduced current consumption in the DRAM by a signal from outside and without causing occurrence of malfunction at times of low current consumption. An input circuit for receiving signals, a memory array for holding data, and a peripheral circuit for controlling the memory array are driven by an internal voltage supplied by two groups of internal voltage receiving circuits while an output circuit for outputting signals is driven by an external power supply. The two groups of internal voltage receiving circuits are deactivated in response to a power supply control signal CONT inputted from outside, and the output circuit is controlled so as to be in a high impedance condition with voltage of the external power supply being applied thereto.

Disclosed herein is an ATD circuit of the present invention. In order to generate a stable ATD pulse, a pulse width amplifier circuit is provided between a first circuit means and a second circuit means. The first circuit means outputs a first output signal having a first pulse width in response to a change in external address signal and outputs, when the external address signal is brought to a first sawtooth signal, a second sawtooth output signal having a peak value smaller than that of the first sawtooth signal. The second circuit means inputs therein the signal outputted from the pulse width amplifier circuit and waveform-shapes the output signal so as to output an ATD signal therefrom. The pulse width amplifier circuit amplifies a pulse width of the signal outputted from the first circuit means. Further, the pulse width amplifier circuit outputs a third output signal having a second pulse width corresponding to the first pulse width when the first output signal is input thereto and outputs a fourth output signal having a third pulse width when the second output signal is input thereto.

Pulse width amplifier circuit

A sense circuit for a DRAM circuit in which small potential difference between bit lines and is produced when the memory cell in the memory cell array is connected to one of the bit lines. The sense circuit starts sensing and amplifying when the sense starting signal changes to 'L' level. An inverter provides a sense activating signal of 'H' level to an NMOS device, while another inverter provides a sense activating signal of 'L' level to a PMOS device. Sense amplifiers 33 are then activated and the potential difference between the bit lines and is amplified. Since the 'L' level of the sense activating signal that is generated by the inverter is set to a value midway between a first power potential VSS and a second power potential VCC, the conductive resistance of the PMOS device is higher than that of a conventional circuit supplied with the first power potential VSS. Consequently, the voltage drop due to the PMOS device increases and power noise is reduced.

Memory device with current limiting feature

In an ATD circuit, a pulse width amplifier circuit is provided between a first circuit means and a second circuit means. The first circuit means generates a first output signal having a first pulse width in response to a change in external address signal and generates, when the external address signal becomes a first sawtooth signal, a second sawtooth output signal having a peak value smaller than that of the first sawtooth signal. The second circuit means receives therein the signal generated by the pulse width amplifier circuit and waveform-shapes the output signal so as to provide an ATD signal therefrom. The pulse width amplifier circuit amplifies a pulse width of the signal generated by the first circuit means. Further, the pulse width amplifier circuit generates a third output signal having a second pulse width corresponding to the first pulse width when the first output signal is received thereto and generates a fourth output signal having a third pulse width when the second output signal is received thereto.

Address transition detector circuit

A semiconductor memory device of the present invention comprises an internal power supplying circuit electrically connected to an external power supply having an external source potential and for supplying an internal potential lower than the external source potential, a precharging circuit for supplying a half potential of the internal potential to each of memory cells and bit lines, and a switching circuit electrically connected between each bit line and the precharging circuit and controlled based on an equalize signal output from a control circuit and having the same potential as the external source potential. The semiconductor memory device of such a type that even if a potential on each bit line increases excessively, such a potential does not exert an influence on each memory cell, can be realized owing to the above structure.

Semiconductor memory device

A semiconductor memory has sense amplifiers which are supplied with a first potential from a first supply line and a second potential from a second supply line. A switching element on the first supply line is controlled by the potential of the second supply line, its conductivity increasing as the potential of the second supply line moves toward the second potential. A similar switching element, controlled by the potential of the first supply line, can be provided on the second supply line.

Semiconductor memory with improved power supply control circuit

A semiconductor memory has sense amplifiers coupled to complementary pairs of bit lines. A first switching element couples the sense amplifiers to a first potential, so that the sense amplifiers can bring one bit line in each pair of bit lines from a precharged state to the first potential. A second switching element couples the sense amplifiers to a shunt node. A third switching element couples the shunt node to the first potential. A capacitor capacitively couples the shunt node to a second potential different from the first potential.

Semiconductor memory with reduced peak current

A semiconductor memory device includes a plurality of bit lines, a plurality of memory cells connected to the bit line. The semiconductor memory device also includes control circuits, a first control line and a second control line. The control circuit outputs a control signal. The first control line is formed by a first low resistance conductive layer and is connected to the control circuit to transfer the control signal. The first control signal extends to a first direction. A second control line is formed by a second low resistance conductive layer which is separated from the first conductive layer by an insulating layer. The second control line is connected to the control circuit to transfer the control signal and extends to a second direction which is substantially different from the first direction.

A semiconductor memory device provided that first data is read out from a first memory cell within a first readout period; and second data is read out from the second memory cell within a second readout period; wherein an amplifier circuit receiving the first and second data, outputting first data signals having first electric potential level corresponding to the first and second data and outputting second data signal having second electric potential level; control circuit, in response to an external control signal, generating a first control signal in each of the first and second readout periods, the first control signal indicating first logic level during an enabling period of time within each of the first and second readout periods, otherwise the first control signal indicating second logic level; a first latch circuit latching the first data signals in the respective first and second readout periods and outputting a first latched data signal at the time of the first control signal indicating the first logic level; a second latch circuit latching the second data signals in the respective first and second readout periods and outputting a second latched data signal at the time of the first control signal indicating the first logic level; and a reset circuit placing the first and second latch circuit in an initial status after the first control signal is transferred from the first logic level to the second logic level in the first readout period and before the first control signal is transferred from the second logic level to the first logic level in the second readout period.

An integrated circuit memory device includes a sense amplifier circuit having a first transistor coupling section connected between a pair of bit lines and a pair of sense amplifier nodes. The first transistor coupling section selectively connects the bit lines and the sense amplifier nodes in response to a first control signal. The sense amplifier circuit further includes a first sense amplifier connected between the sense amplifier nodes so as to selectively discharge one of the sense amplifier nodes and a second sense amplifier connected between the sense amplifier nodes so as to selectively charge the other one of the sense amplifier nodes. The first control signal can have a first voltage substantially intermediate a potential equal to a potential threshold of a transistor in the first transistor coupling section and the sum of a potential equal to the potential threshold and a precharge potential at the beginning of a sense operation. At these voltage levels, the first transistor is operative to decouple a first sense node from a first bit line when a selected memory cell stores a logic ONE level while a second transistor connects a second sense node with as second bit line. Also, the second transistor is operative to decouple the second sense node from the second bit line when the selected memory cell stores a logic ZERO level while the first transistor connects the first sense node with the first bit line.

Sense amplifier circuitry selectively separable from bit lines for

An MOS semiconductor memory device includes memory cell matrices. Each matrix is constituted with memory cells and noise cancellers. Each memory cell is connected, at an intersection between a pair of bit lines and a word line, between either one of the bit lines and the word line. The word line controls read and write operations of the memory cell. The noise canceller is connected, at an intersection between a pair of bit lines and a dummy word line, between either one of the bit lines and the dummy word line. The dummy word line enables the noise canceller. The memory cell matrices form groups of memory cells into which the cells are grouped in accordance wtih addresses. The dummy word line and the word line have substantially identical characteristics. The dummy word line possesses parasitic resistance and capacitance to delay by a first predetermined period of time a signal to enable the noise canceller. The memory device further includes sense amplifier circuits connected between the pair of bit lines of the memory cell matrices for amplifying a potential difference between the bit lines in response to an enable signal, and a sense control circuit connected to the dummy word lines and the sense amplifier circuits to be operative in a read or write operation of the memory cell for selectively enabling related sense amplifier circuits in response to a signal delayed by a dummy word line of selected ones of the memory cell matrices.

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Tokyo, Japan

Junichi Suyama