Yanchers Corporation

Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Nichia Corporation

Junichi Shimada

Yoichi Kawakami

Kiyohito Mukai

Mitsumi Ito

Motokazu Yamada

Hiroyuki Tsujikawa

Fumihiro Kimura

Hiromasa Fukazawa

Takeya Fujino

Nobuyuki Iwauchi

Hidenori Shibata

Masaru Kato

Tsutomu Fujii

Takuya Yasui

Yoichi Matsumura

Takako Ohashi

Yukiji Hashimoto

Hirofumi Taguchi

Takayuki Araki

A novel therapeutic agent for solid cancer capable of hardening the cellular tissue itself of a solid cancer to induce death or growth inhibition of cancer cells, causing solidification of the tissue, is disclosed. The therapeutic agent for solid cancer is composed of a liquid composition containing as an active component an ethoxy-containing compound capable of undergoing polycondensation in a cellular tissue. The therapeutic agent for solid cancer is capable of hardening the cellular tissue itself of a solid cancer such as lung cancer to induce death or growth inhibition of cancer cells, causing solidification of the tissue. In conventional therapeutic methods, the risk of metastasis due to spreading of cancer cells through the bloodstream cannot be eliminated. In contrast, this therapeutic agent for solid cancer instantly surrounds cancer cells, so that the risk of metastasis can be largely reduced.

Therapeutic agent for solid cancer

A first dummy via pattern having high density is arranged in the vicinity of first and second wirings on a semiconductor device, and a second dummy via pattern having low density is arranged in a distant region from the first and second wirings, with reference to the first dummy via pattern. Accordingly, it is possible to suppress expansion of the file size of layout CAD data due to dummy vias, while complying with a design standard regulated for each semiconductor process, regardless of the presence or absence of vias which connect the first wirings to the second wirings.

Semiconductor device

Disclosed is a semiconductor device having a multilayer wiring structure, in which a dummy pattern is formed in a wiring void with favorable manufacturing efficiency. In a semiconductor device having a multilayer wiring structure, dummy pattern () is formed in relatively narrow wiring void (Area_S) so as to extend in a direction different from that of dummy patterns () formed in relatively wide wiring void (Area_S).

A semiconductor device including a plurality of cells having an antenna protection element and a cell other than the antenna protection element; and a first dummy pattern and a second dummy pattern arranged in a layer above the plurality of cells. Further, the first dummy pattern overlaps with the antenna protection element, the second dummy pattern overlaps with the cell other than the antenna protection element, and a first layout rule of the first dummy pattern is different from a second layout rule of the second dummy pattern.

Semiconductor device and semiconductor device layout designing method

The present invention is achieved with the object of providing an illumination system formed of an LED light emitting body and a socket which can appropriately release heat from LED chips. This object is achieved in the following manner. A heat conducting layermade of diamond is provided on a substrate, and on top of this, a conductive layerhaving a predetermined pattern is formed. LED chipsare mounted in predetermined positions on the conductive layer. Terminals of the conductive layerand electrodes of the LED chipsare connected to each other. A connector partfor the connection to a socket is provided in an end portion of the substrate. The heat conducting layeron the connector partmakes thermal contact with the heat conducting layer provided on the inner surface of the opening of the socket. A current is supplied to respective LED chipsthrough the conductive layerfrom the socket, and respective LED chipsemit light. Heat that is generated in the LED chipsis released to the outside of the illumination system from the socket through the conductive layer, the heat conducting layerand the connector part. As a result of this, an increase in the temperature of the LED chipscan be prevented, and an LED illumination system that emits a large amount of light can be formed.

LED illumination system

The lighting system according to the present invention includes an electrical wiring substrate in which a connector to a power source is formed, a plurality of LED chips mounted in a predetermined array pattern on the electrical wiring substrate, a deflection lens array disposed in proximity to the LED chips between the LED chip and the predetermined illumination region and a housing for receiving the electrical wiring substrate and the deflection lens array. A plurality of deflection lenses are integrally molded in the deflection lens array to lead lights from the LED chips to the predetermined illumination region in a state where the lights from the LED chips are superposed with each other. The lights emitted from the LED chips are collected in a state where they all are superposed in a common, single illumination region through the deflection lenses.

Lighting system

A lighting apparatus which improves identification of living body tissues, and is suitable for medical lighting. In the lighting apparatus, the light output in a range of wavelength 525 to 590 nm is not greater than &#x2155; of the light output in a range of wavelength 380 to 780 nm corresponding to visible light components. The peak wavelength of a blue or bluish green light component included in the output light is in a range of 430 to 520 nm, and the peak wavelength of a red light component is not less than 600 nm. A green light component has the peak in a range of wavelength 520 to 590 nm, its spectral half-value width is not greater than 70 nm, and the light amount of at least the green light component can be independently adjusted.

Lighting apparatus with filter

Verification of the pattern area ratio of a semiconductor integrated circuit device or the pattern occupancy ratio in a check window set for the semiconductor integrated circuit device is performed on an assumption that a dummy pattern defined by process conditions is placed in an unoccupied region of the semiconductor integrated circuit device or in an unoccupied region in at least one instance provided in the semiconductor integrated circuit device.

Area ratio/occupancy ratio verification method and pattern generation method

To provide a pattern generating method for a semiconductor device capable of forming a highly reliable semiconductor device, the accuracy of which is high. A method of generating a pattern for a semiconductor device comprises: a step of designing and arranging a layout pattern of a semiconductor chip; a step of extracting an area ratio of the mask pattern from the layout pattern; and a step of adding and arranging a dummy pattern to the layout pattern, while consideration is given to the most appropriate area ratio of the layout pattern of the layer obtained according to a process condition of the layer composing the layout pattern, so that the area ratio of the layer can be the most appropriate area ratio.

Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor device

To provide a semiconductor device characterized in that: a decoupling capacitor can be increased; noise generated from an electric power supply can be effectively absorbed; and a stable operation of a circuit can be realized. Irrespective of whether or not a region is close to a power supply wiring or a ground wiring, MOS is spread all over a spare area of a chip and connected to a power supply wiring and ground wiring by utilizing a wiring layer and diffusion layer.

Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device for generating pattern used for semiconductor device

Growing community of inventors

Kyoto, Japan

Junichi Shimada