Alps Electric Co., Ltd.

Other

Alpine Electronics, Inc.

Junichi Saito

Yuichi Umeda

Masatoshi Uchio

Arao Sato

Tatsumi Fujiyoshi

Yukimitsu Yamada

Ichiro Morishita

Masaru Nakayama

Kazuyoshi Yamagata

Kazuhiro Katagiri

Hiroyuki Hebiguchi

Ken Kawahata

Tomoyuki Sawataishi

Tomomitsu Muta

Masahiro Tanaka

Masahiko Morinaga

Yoshinori Murata

Akira Asao

Kisei Hirobe

Satoshi Inoue

Yuichi Yasuda

Shigeki Kano

Yoshiaki Tachi

Mitsuaki Furui

A sensor chip includes sensor pads, and the first set of differential detection signal pads are symmetrically arranged on both sides of a ground pad and are centered at the ground pad, the second set of differential detection signal pads are arranged on both sides thereof, and a power supply pad is arranged in one end of the two ends of the sensor pads. A processing circuit chip includes sensor connection pads including power supply connection pads, a ground connection pad, and two sets of differential detection signal connection pads, and the power supply connection pads connectable to the power supply pad of the sensor chip are arranged in two ends of the sensor connection pads.

Sensor module, and sensor chip and processing circuit chip used therefor

A semiconductor integrated circuit device is configured such that if, due to an erroneous connection or the like, an abnormal state is entered in which an output voltage is lower than a ground potential VSS, an N-type DMOS transistor and a first P-type MOS transistor are turned off and a voltage is applied to their parasitic diodes in the opposite direction, preventing a current from flowing. In a normal state in which the output voltage is higher than the ground potential, at least one of the N-type DMOS transistor and first P-type MOS transistor, which are connected in parallel, is turned on, preventing a current from flowing into the parasitic diode of the N-type DMOS transistor.

Semiconductor integrated circuit device

The highest voltage of a power supply voltage, a ground potential, and a signal voltage is output as a selection voltage from a terminal on the output side. In this case, terminals on the input side and the terminal on the output side are connected to each other through MOS transistors in the ON state. Therefore, it is possible to suppress a voltage drop due to a parasitic diode of each MOS transistor.

Voltage selection circuit and semiconductor integrated circuit device having the same

A constant-voltage circuit includes a first reference voltage generation unit which generates a reference voltage using a bandgap voltage of a bipolar transistor, a second reference voltage generation unit which generates a reference voltage using a field effect transistor, a constant voltage generation unit which generates a constant voltage with reference to either an output voltage of the first reference voltage generation unit or an output voltage of the second reference voltage generation unit, and a control unit which controls the first reference voltage generation unit, the second reference voltage generation unit, and the constant voltage generation unit. During an initial activation period, the first reference voltage generation unit and the second reference voltage generation unit are operated, and during a subsequent operation period, the first reference voltage generation unit is stopped.

Constant-voltage circuit

A sampling rate conversion apparatus and a method thereof are provided which increase the sampling rate of a discrete audio signal sampled at a predetermined sampling rate by using a fractal interpolation function (FIF). An audio signal portion formed by a predetermined number of sampling data items is divided into a plurality of interpolation intervals. On the audio signal portion, mapping points are determined. The number of the mapping points is in accordance with the degree of increase in the sampling rate. For the respective interpolation intervals, mapping parameters for performing mapping using the FIF on the mapping points are calculated. In all of the interpolation intervals, the mapping using the FIF is performed on the mapping points with the use of the mapping parameters according to the respective interpolation intervals. Thereby, new sampling data items are generated.

Sampling rate conversion apparatus and method thereof

A capacitance detecting circuit includes a code generator for generating code having orthogonality in chronological order. A column-line driver drives the plurality of column lines based on the code by dividing the column lines into a first column line group and a second column line group. A capacitance detector, which is connected to the row line, converts the total of currents generated in capacitances at the intersections with the driven column lines into a voltage signal and outputs the converted voltage signal. A decoding computation unit determines the voltages corresponding to the capacitances at the intersections for each of the column line groups by performing product sum computation between the measured voltages and the code. The column-line driver drives the first column line group and the second column line group by complementary voltages according to the code or information indicating the inversion of the code.

Capacitance detecting circuit and method, and fingerprint sensor using the same

In a capacitance detecting circuit, changes in capacitances at intersections between a plurality of row lines and a column line are detected as voltages. The capacitance detecting circuit includes a column-line driver for driving the column line. A code generator generates code having orthogonality in chronological order. A selection synthesizer selects a certain number of row lines from the plurality of row lines by using the code and synthesizes measured voltages at the intersections between the selected row lines and the driven column line so as to output the synthesized measured voltage. A decoding computation unit separates the measured voltages corresponding to the capacitances at the intersections by performing product sum computation between the synthesized measured voltage and the code.

An analog Y signal input from an input terminalis clamped at a pedestal level in a clamp circuit, and then, is converted to a digital image signal in a quantization circuit. The pedestal level Dp of the digital output D(t)is stored in a register. A predetermined value Dref (Dref=0 for the Y signal) is subtracted from Dp in a subtracter. The subtraction outputis subtracted from the digital outputin a subtracter. The subtraction output(D(t)&#x2212;(Dp&#x2212;Dref)) is a signal for which a shift caused by a variation in the precision of the clamp circuitand the quantization circuithas been compensated for. The subtraction outputis limited to a predetermined dynamic range by an overflow limiter circuit, and output as Dout.

Image-signal processing apparatus for clamping analog image signal and then for converting it to digital image signal

A display device includes, on a first substrate of a pair of substrates, data lines and scanning lines crossing in the form of a matrix. Among the data lines, a first group of data lines lead to a first side of the first substrate, and a second group of data lines, other than the first group of data lines, lead to a second side positioned opposite to the first side. The display device includes a display screen in which the surface of the one substrate is divided into dots by the data lines and the scanning lines and each set of a predetermined number of adjacent dots constitutes each pixel. All data lines which are connected to the predetermined number of adjacent dots constituting the pixel in the display screen lead to a single side among the sides of the first substrate.

Display device requiring no scramble circuit

An image display device includes a display panel having predetermined numbers of pixels defined in horizontal and vertical directions, respectively, and an interpolated-data generation circuit whereby an expanded image data is produced in such a manner that when the number of pixels in the horizontal direction of the display panel is greater than the number of pixels in the horizontal direction of a given image signal, the interpolated-data generation circuit directly stores a plurality of image data A, B, C, D, E of the original image signal along one horizontal line at data storage locations closest to the original locations, and data at data storage locations remaining after storing all original data are given the results X, Y, and Z obtained by calculation from two original image data at locations adjacent to the respective remaining data storage locations thereby expanding the original image signal to have a resolution well matched to the resolution of the display panel without causing a reduction in contrast.

Image display device and driver circuit therefor

Image expansion display and driver

Super heat-resisting Mo-based alloy and method of producing same

In a relative angle detecting device, plural received light outputs are subjected to time division. Received light detection voltage is shifted by a phase shifter and sampling pulse is formed, and peak detecting means holds peak value of received light output based on the sampling pulse. In a CPU, peak value of each voltage is stored in a memory, and the stored value is operated thereby information regarding relative position between a light source and a light reception element is operated. Utilizing the time division, each received light detection voltage can be processed in the same condition, and the peak value of each received light output can be detected with high precision.

Relative angle detecting device

A pair of detecting stations A.sub.i and A.sub.-i on a plane H extends along an axis X. Each of the detecting stations is provided with an iris member and a divided light receiving section. Received light outputs at each of the light receiving elements are defined as R.sub.i, L.sub.i, R.sub.-i, and L.sub.-i, and the following equation is calculated to enable a coordinate (x.sub.0, z.sub.0) of the moving light source to be attained by a simple calculation: S.sub.i =(R.sub.i -L.sub.i)/(R.sub.i +L.sub.i)+(R.sub.-i -L.sub.-i)/(R.sub.-i +L.sub.-i); T.sub.i =(R.sub.i -L.sub.i)/(R.sub.i +L.sub.i)-(R.sub.-i -L.sub.-i)/(R.sub.-i +L.sub.-i).

Coordinate position of moving light source by using separated groups of

An apparatus is disclosed for inclination detection wherein infrared transmitted signal, signal groups S1, S2, S3, . . . including a leader code, a parity bit and bits for data transfer are sequentially transmitted with an interval time t3. At each bit of the signal group S1, '1' and '0' of a binary signal expressing the data are not inverted, at the signal group S2, '1'and '0' expressing the data are inverted, and inversion and non-inversion are repeated every signal group. At bits of each signal group, since a time length expresses '1' and '0', a total time length of each signal group is different from that of other signal group. By repeating sets of inverted and non-inverted signal groups, the time length of each set is averaged, and hence, data processing can be made more efficient.

Growing community of inventors

Miyagi-ken, Japan

Junichi Saito