Kabushiki Kaisha Toshiba

Thine Electronics, Inc.

Trigence Semiconductor, Inc.

Pioneer Corporation

Increment P Corporation

Trigence Semiconductors, Inc.

Junichi Okamura

Tohru Furuyama

Tetsuya Kaneko

Akira Yasuda

Seiichi Ozawa

A digital/analog conversion apparatus to convert a digital signal into an analog signal. The digital/analog conversion apparatus can generate a high-quality analog signal, even when elements configuring the digital/analog conversion apparatus have variance, with high resolution and a small circuit size. The data conversion apparatus is provided with a first data converter to reduce the number of bits of an input signal, a second data converter to convert the format of the first output signal, and a third data converter for conversion into a code which corresponds to the history of the output from the second data converter.

Digital/analog conversion apparatus

Digital/analogue conversion apparatus

A digital/analog conversion apparatus for converting a digital signal into an analog signal. The digital/analog conversion apparatus can generate a high-quality analog signal, even when elements configuring the digital/analog conversion apparatus have variance, with high resolution and a small circuit size. The data conversion apparatus is provided with a first data converter for reducing the number of bits of an input signal, a second data converter for converting the format of the first output signal, and a third data converter for conversion into a code which corresponds to the history of the output from the second data converter.

A map database site S comprises a map information database Sb for accumulating the map data constructed of units for displaying of unit images m each having a display range smaller than a display range of a map image M corresponding to one page of a map image displayed on a user terminal T, in association with position data indicating the display ranges of the individual unit images m. A user terminal T comprises map-image display means for combining the map data of a plurality of units with each other on the basis of the associated position data, which are read out from the map information database Sb provided in the map database site S and transmitted from the map database site S, to form the one-page map image M for display.

System and method of displaying map image

A semiconductor integrated circuit in which multiphase clock signals having the same phase difference are supplied from a multi-stage differential ring oscillator to other circuits, the multiphase clock signals can be prevented from being degraded in waveform due to electrostatic coupling between wirings of the multiphase clock signals and also wired in as small an area as possible. The semiconductor integrated circuit includes: multiple stages of amplifier circuits, connected in a ring form, for performing oscillating operation; a logic circuit for performing logic operation on the basis of predetermined ones of output signals of the multiple stages of amplifier circuits to output a plurality of clock signals having different phases from each other and duties not equal to 0.5; and a plurality of wirings for transmitting the plurality of clock signals output from the logic circuit.

Semiconductor integrated circuit

A semiconductor integrated circuit in which, when leading out multiple-phase clock signal wirings from the ring oscillator circuit capable of oscillating at a high frequency, increase in the area of the substrate and deterioration in the clock phase accuracy caused by the non-uniform stray capacitances among the multiple-phase clock signal wirings are prevented. The semiconductor integrated circuit includes: N-stage amplifying circuits connected in a form of a ring to perform oscillating operation, which amplifying circuits are arranged in a semiconductor substrate to be divided into a plurality of rows, wherein in each row an amplifying circuit of 'm&#x2212;1'th stage and an amplifying circuit of 'm'th stage are not adjacent to each other, where m is an arbitrary integer number within a range from 2 to N; and a plurality of wirings for respectively leading out a plurality of output signals from the amplifying circuits disposed in one of the plurality of rows.

Semiconductor integrated circuit with wiring arrangement for N-stage amplifying

A phase-selective type frequency modulator capable of easing the restriction on a phase range of a modulated clock signal. The phase-selective type frequency modulator includes a multiphase clock signal generating circuitfor generating N-phase clock signals; a control circuitfor sequentially activating one of first group of clock selection signals indicating a clock signal to be selected from the N-phase clock signals; an edge appearance time adjustment circuitfor adjusting a rising edge appearance time and/or a trailing edge appearance time of the first group of clock selection signals outputted from the control circuitto output second group of clock selection signals; and a modulated clock signal generating circuitfor selecting one clock signal from the N-phase clock signals in accordance with an activated state of the second group of clock selection signals outputted from the edge appearance time adjustment circuitto output a modulated clock signal MCK.

Frequency modulator apparatus of phase selection type, and frequency synthesizer of phase selection type

In a semiconductor integrated circuit including a phase comparison circuit for a DLL in a reception circuit for receiving serial digital transmission signals, phase detection characteristics of the phase comparison circuit are improved while preventing false lock so as to improve response speed and locking accuracy of the DLL as a whole. The semiconductor integrated circuit includes series-connected delay elements each having a delay time which is controlled in accordance with a control voltage, a phase comparison circuit for generating a voltage corresponding to a phase difference between a clock signal input to a predetermined one of the delay elements and a clock signal output from another predetermined one of the delay elements, a control circuit for controlling the phase comparison circuit to generate a predetermined voltage when said phase difference is within a predetermined range, and a filter circuit for filtering the voltage generated by the phase comparison circuit to generate the control voltage to be applied to the delay elements.

A semiconductor integrated circuit which realizes a reception circuit that can stably detect symbol values even in a case where, in the reception of serial transmission data, the serial transmission data has its phase shifted relative to the sampling clock signals or has its waveform degraded due to the deviation of the delay of a signal in a transmission line. The semiconductor integrated circuit comprises a first clock-signal generating circuit which generates a clock signal of N phases synchronized with an input clock signal, a second clock-signal generating circuit which generates a clock signal of M phases synchronized with one phase selected from among the N-phase clock signal generated by the first clock-signal generating circuit, and in which N&#x2260;M holds, and a computation circuit which finds a control value for use in selecting one phase from among the N-phase clock signal, on the basis of the logic value of the serial transmission data sampled using the N-phase clock signal and the M-phase clock signal.

A voltage generator for outputting an output voltage at an output terminal thereof includes a driver MOS transistor of a first conductivity type having a first end connected to said output terminal and a capacitor connected between the output terminal and a second voltage node. The capacitor comprises a plurality of trench capacitors formed in a semiconductor substrate.

Voltage generator for semiconductor device

A dynamic random access memory includes a plurality of dynamic memory cells arranged in rows and columns, a word line connected to the memory cells on the same row, a bit line connected to the memory cells on the same column, a word line selecting circuit having a word line selecting function of selecting an arbitrary one of the rows in response to an internal address signal, a word line driving voltage source, a word line driving circuit having at least one driving MOS transistor connected between the word line driving voltage source and the word line, for driving the word line in response to an output signal of the word line selecting circuit, and a control circuit for, in response to a voltage stress test control signal input from outside, controlling the word line driving circuit so that the word line driving circuit drives word lines more than those selected in a normal operation mode upon receiving an external address signal.

Dynamic random access memory

A semiconductor memory device includes a memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor, a word line connected to a gate of the transfer N-channel transistor, of the memory cell, a charge pump circuit generating an internal power supply voltage which is boosted up from a power supply voltage, and outputting the internal power supply voltage, and a decoder circuit which receives address signals and has a P-channel MOS transistor for receiving the internal power supply voltage, the decoder circuit generating a word line selecting signal. Also, the semiconductor memory device includes a word line driving circuit for driving a corresponding word line in accordance with the word line selecting signal, the word line driving circuit being provided in correspondence with the word line and having a first MOS transistor and a second MOS transistor, the first MOS transistor having a first current path, a first end of the first current path being connected to a first node having the internal power supply voltage, a second end of the first current path being connected to the word line and a gate which is controlled in accordance with the word line selecting signal, the second MOS transistor having a second current path, a first end of the second current path being connected to the first MOS transistor, a second end of the second current path being connected to a predetermined potential lower than the internal power supply voltage, wherein the charge pump circuit outputs the internal power supply voltage for a first period in which at least the P-channel MOS transistor is in an ON state and a second period in which at least the first MOS transistor is in an ON state.

A dynamic random access memory includes a dynamic memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor, a word line connected to a gate of the transfer N-channel transistor, of the dynamic memory cell, and a word line driving voltage source, to which power voltage is input for raising the input power voltage to generate a word line driving voltage. Also, the dynamic random access memory includes an address circuit for generating internal address signals in accordance with externally input address signals, a word line selecting circuit for decoding the internal address signals and outputting a word line selecting signal which varies within a range between the word line driving voltage and a ground potential, and a word line driving circuit for driving a corresponding word line in accordance with the word line selecting signal, the word line driving circuit being provided in correspondence with the word line and having a P-channel MOS transistor which has a source connected to a first node having the word line driving voltage, a drain connected to the word line and a gate to which the word line selecting signal is applied.

Growing community of inventors

Tokyo, Japan

Junichi Okamura