Renesas Technology Corp.

Hitachi, Ltd.

Renesas Electronics Corporation

Other

Hitachi Ulsi Systems Co., Ltd.

Hitachi Engineering Co., Ltd.

Semiconductor Technology Academic Research Center

Hitachi Ulsi Engineering Corp.

Junichi Nishimoto

Kenji Hirose

Hideaki Abe

Tadashi Hoshi

Midori Nagayama

Koji Yamada

Toshihiro Hattori

Takuichiro Nakazawa

Koichiro Ishibashi

Susumu Narita

Yasuhisa Shimazaki

Shinichi Yoshioka

Masayuki Ito

Seiichi Nagata

Katuhiro Norisue

Masakazu Aoki

Masanao Yamaoka

Kazumasa Yanagisawa

Shoji Shukuri

Hideo Maejima

Makoto Toda

Kunio Uchiyama

Ikuya Arai

Osamu Nishii

Fumio Arakawa

Kozo Masuda

Kazuyuki Takizawa

Tatsuya Kamei

Yasuhiro Tawara

Ken Tatezawa

Masayuki Arai

Kazuhiko Iwasaki

Satoshi Fukumoto

Takeshi Shoda

Jun Hasegawa

Yutaka Yoshida

One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.

Data processing system and data processor

A mobile telephone is provided that includes a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The mobile telephone also includes an interblock interface circuit provided on a signal path between an elected circuit block and a branch point at which the signal path branches into different branch paths so as to connect to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission from the elected circuit block to the other circuit blocks, and includes a storage unit for storing a signal right before the power cut-off.

Multiple circuit blocks with interblock control and power conservation

A communication terminal apparatus which improves the a quality of an additional function such as image processing, music reproduction etc. over repressing power consumption is provided. The communication terminal apparatus has a transmission and reception unit adapted to transmit or receive a signal including a voice signal or an image signal, a decode processing unit adapted to decode a received signal, a first control circuit for controlling the transmission and reception unit and the decode processing unit, a second control circuit for processing an image signal which is outputted from the decode processing unit, a first power supply unit adapted to supply electric power to the first control circuit, and a second power supply unit adapted to supply electric power to the second control circuit, and in case that the communication terminal apparatus is not operated for a given length of time, the second power supply unit reduces electric power to the second control circuit.

Communication terminal apparatus

Mobile telephone with interblock control for power conservation

An object of the invention is to drastically reduce the area overhead in a semiconductor integrated circuit incorporating a test configuration that uses a partially rotational scan circuit. To achieve this, in the semiconductor integrated circuit incorporating the test configuration that comprises a combinational circuit () and a scan chain () constructed by connecting a plurality of scan flip-flops () in a chain, the scan chain () is divided into a plurality of sub scan-chains (to) each of which has a partially rotational scan (PRS) function and a test response compaction (MISR) function. By performing a scan test in a plurality of steps while changing the combination of the sub scan-chains to be set as PRS and the sub scan-chains to be set as MISR, the test can be performed without having to provide a test response compactor separately from the scan chain, and thus the area overhead can be reduced.

Semiconductor integrated circuit incorporating test configuration and test method for the same

A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path between an elected circuit block and a branch point at which the signal path branches into different branch paths so as to connect to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission from the elected circuit block to the other circuit blocks, and includes a storage unit for storing a signal right before the power cut-off.

A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path from the elected circuit block to other circuit blocks, wherein a single output of the interblock interface circuit is branched out to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission to other circuit blocks and includes a storage unit for storing a signal right before the power cut.

Growing community of inventors

Hachioji, Japan

Junichi Nishimoto