Sony Computer Entertainment Inc.

Sony Interactive Entertainment Inc.

Sega Enterprises, Ltd.

Kabushiki Kaisha Toshiba

Junichi Naoi

Satoru Matsuda

Masanori Nomura

Tomohiro Ogawa

Takenori Oshima

Seisuke Morioka

Akio Ohba

Masaaki Oka

Atsushi Kunimatsu

Masaki Takase

Keisuke Yasui

Jiro Amemiya

Jun Okubo

Junichi Asano

Tomohiro Ohto

The present invention is intended to realize character string input using two or more devices by an efficient technique. A character string input system includes a first information processing apparatus and a second information processing apparatus. The first information processing apparatus acquires an operation done on a first input device and acquires a first character string on the basis of the acquired operation. The second information processing apparatus acquires an operation done on a second input device and acquires a second character string on the basis of the acquired operation. The first information processing apparatus outputs an input character string on the basis of the first character string acquired by the time input of the second character string is started by use of the second input device and the second character string.

Character string input system

The operability is improved when an operation for moving a cursor to a target position is carried out by a controller which outputs operation amount data associated with an operation amount vector representative of a direction and a magnitude of the operation. An operation amount component specification unit specifies, on the basis of the operation amount data, the magnitude of a first operation amount component and the magnitude of a second operation amount component. A movement amount component determination unit determines the magnitude of a first movement amount component and the magnitude of a second movement amount component. A cursor position changing unit changes the position of the cursor from a current position of the cursor to a position spaced by the magnitude of the first movement amount component in a first disposition direction and spaced by the magnitude of the second movement amount component in a second disposition direction. The disposition distance between the choices along the second disposition direction is shorter than the disposition distance between the choices along the first disposition direction. The ratio of the magnitude of the second movement amount component to the magnitude of the second operation amount component is smaller than the ratio of the magnitude of the first movement amount component to the magnitude of the first operation amount component.

Cursor position controlling apparatus, cursor position controlling method, program and information storage medium

An entertainment device includes a general-purpose signal processor made up of an assembly of component-processors, each of which can operate in parallel under operating environments independent of others component-processors. A management processor controls a cross bar so as to change the operating environments of the respective component-processors in accordance with a demand for signal processing which is given from a CPU, and to change over any one of the component-processors which receives a signal to be processed which is inputted through the cross bar or outputs a processed signal in accordance with the demand for signal processing.

Configuring selected component-processors operating environment and input/output connections based on demand

A DDAnotifies the coordinates of a rasterized pixel to an exclusive control part, acquires a unique identification number associated with the pixel position from the exclusive control part, and adds the identification number to pixel data and supplies it to a shader. A plurality of shader pipesin the shaderperform arithmetic processing for rendering pixels in parallel, and writes the processing results to a frame buffer. When performing an arithmetic instruction that requires exclusive control over a pixel, each shader pipeissues a request to lock the pixel by notifying the identification information added to that pixel to the exclusive control part. If the lock request is accepted, the shader pipeperforms the arithmetic processing on that pixel. If the lock request is rejected, the shader pipe suspends and puts the arithmetic processing on that pixel into a wait state, and executes arithmetic processing on another pixel in the interim.

Rendering processing apparatus, parallel processing apparatus, and exclusive control method

Registers-hold data for pixels interleaved. An operatorreads the pixel data from the registers and processes the pixel data in accordance with a program code. The operatorwrites the result of the process back to the registers via a cacheor writes it in a memory. Program counters PC-PCprovided in association with the number of pixels interleaved store the addresses of instructions in a program for the respective pixels. An instruction loaderalternately reads from the program counters. An incrementerincrements the count of the program counters. The instructions in the program for the pixels are alternately loaded and interleaved on a pixel by pixel basis, before being supplied to the operatorand the like.

Graphics processor, graphics processing method, information processor and information processing method

A rendering processing apparatus is provided which performs occlusion culling for excluding from rendering targets a hidden object behind another object as seen from a point of view, when given a plurality of objects. An object input unit stores a plurality of objects in an object storing unit. An internal volume generating unit generates an internal volume which is included in a target object. A reduced Z-buffer updating unit updates a reduced Z-buffer based on the internal volume. An external volume generating unit generates an external volume which includes the target object subject to culling test. A culling determination unit consults the reduced Z-buffer and performs a Z culling test on the target object based on the external volume.

Occlusion culling method and rendering processing apparatus

Reduced Z-buffer generating method, hidden surface removal method and occlusion culling method

A drawing processing apparatus capable of executing a drawing processing program having conditional branches efficiently by multipass rendering. The drawing processing apparatus comprises arithmetic processing parts including an object input part, a primitive generating part, a raster part, a pixelation part, a distribution part, and a shader which constitute pipeline stages. The shader divides the program into and executes the same in a plurality of passes depending on conditional branches. The shader generates enable flags determining whether or not respective pixels satisfy branch conditions. The flag generating part generates bind enable flags which are the enable flags on the pixels bound into the processing granularities of the pipeline stages, and feeds back the same to the respective pipeline stages. The arithmetic processing parts in the individual pipeline stages refer to the bind enable flags and limit the submission of data not targeted for arithmetic processing in the branched passes.

Drawing processing apparatus and drawing processing method for multipass rendering

A shader sends a 'completely full' signal to a buffer control unit when a head pixel in a first pass input from a DDA arrives at a final stage of a pipeline process. When the head pixel in the first pass arrives at a stage in the middle of the pipeline process, the shader sends an 'almost full' signal to the buffer control unit and a primitive generating unit. Upon receiving the &#x201c;almost full&#x201d; signal, the primitive generating unit suspends the generation of rendering primitives in the first pass and starts generating rendering primitives in the second pass. Upon receiving the &#x201c;almost full&#x201d; signal, the buffer control unit supplies the rendering primitives in the first pass from the setup processing unit to the DDA via a temporary buffer. Upon receiving the &#x201c;completely full&#x201d; signal, the buffer control unit switches to a second pass and directly supplies the rendering primitives in the second pass from the setup processing unit to the DDA.

Rendering processor, rasterizer and rendering method

A small cost-effective crossbar switch is provided. A switch circuit is disposed in each of a plurality of nodes which are cascade connected with each other in a plurality of stages. Each switch circuit receives from a node of a previous stage a designated address to specify directly or indirectly the relative position in which a target switch circuit is present, determines whether the designated address represents a specific value '0'. When it is determined that the specific value is represented, each switch circuit allows data output to a node-out line, decrements the received designated address by '1' to generate a new designated address, and supplies this new designated address to a node of the subsequent stage.

Crossbar switch, method for controlling operation thereof, and program for controlling operation thereof

A general-purpose serial operation pipeline realizes a complicated processing flow with an extemporaneous and explosive amount of operations with respect to various data sizes. A plurality of arithmetic-logic circuits (SALCs) that are controlled individually, and that can be operated together with another arithmetic-logic circuit (SALC) are connected in a cascade manner to form a serial operation pipeline. At least one of the plural SALCs includes a line for outputting data from an upstream SALC to a downstream SALC, a line for feeding back reverse data from the downstream SALC to the upstream SALC, and latch circuits for latching the data on the respective lines, thereby being capable of feeding back data from an arbitrary SALC to another SALC.

Serial operation pipeline, arithmetic device, arithmetic-logic circuit and operation method using the serial operation pipeline

The size of polygons for composing an object in computer graphics is compared with a predetermined threshold value. Each polygon not exceeding the threshold value is directly converted into pixels. On the other hand, each polygon having a size which exceeds the threshold value is divided, and the resultant polygons are compared again. This ensures efficient processing of the polygons without causing an expansion of the circuit configuration or a significant increase in cost. The processing of the polygons will never be affected by the size of the polygons.

Image processing method

Disclosed are an antialiasing method and an image processing apparatus using the same, capable of high-quality image display without any significant reduction in processing speed and without any significant increase in the apparatus scale. Pixel data contains information on a subpixel mask indicative of region which a polygon occupies within a pixel. Based on data sets consisting of the subpixel masks and color data contained in the pixel data, display colors are determined on a pixel-by-pixel basis.

Growing community of inventors

Tokyo, Japan

Junichi Naoi