Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Junichi Naka

Koji Oka

Koji Sushihara

Toshiaki Ozeki

Takuji Miki

Yoshitsugu Inagaki

Kenji Murata

Heiji Ikoma

Naoya Yosoku

Masao Takayama

Daisuke Nomasaki

Masakazu Shigemori

Tsuyoshi Matsushita

Youichi Okamoto

Hiroshi Sakura

Yoichi Okamoto

An A/D converter includes: an input buffer; N sub-A/D converters including N first sampling circuits that are connected to the input buffer, and that sample the output analog signal in respective sampling slots; a control circuit that executes calibration for the N first sampling circuits one by one; a reference A/D converter including a second sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slot as the sampling slot of one first sampling circuit under execution of the calibration among the N first sampling circuits; and a third sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slots as the sampling slots of the (N&#x2212;1) first sampling circuits out of the execution of the calibration.

A/D converter including multiple sub-A/D converters

A time-interleaved analog-to-digital (AD) converter includes: N AD converters; a frequency divider that receives a clock signal and applies 1/N frequency division N to the received clock signal to generate N frequency-divided clock signals to be supplied to the N AD converters; at least (N&#x2212;1) variable delay circuit that adjusts delay time for at least (N&#x2212;1) frequency-divided clock signal; a low pass filter circuit or an input buffer circuit that receives the clock signal and limits a frequency band of the received clock signal to generate a reference signal; and a control circuit that controls the delay time of the at least (N&#x2212;1) variable delay circuit, and decreases one or more differences among digital output values output from the N AD converters when the reference signal is input to the N AD converters.

Time-interleaved analog-to-digital converter

It is intended to provide an AD converter capable of increasing its conversion accuracy. An AD converter is equipped with a clock generator which generates a first clock using a second clock and a comparator which includes a comparison circuit for comparing an input signal with a prescribed value in a first period of the first clock and a precharging circuit for precharging, in a second period of the first clock, an internal voltage to a prescribed value for the next comparison operation. The clock generator includes a replica circuit of the precharging circuit of the comparator. In the replica circuit of the precharging circuit, a precharging period from the start to the end of precharging is set as the second period of the first clock.

AD converter and receiving apparatus

Increase of power consumption is reduced, and the operational speed is improved. A comparator includes a comparing section which outputs a result of comparison between a first voltage and a second voltage which constitute an input differential signal, a first positive feedback section which operates in synchronism with a first clock signal, amplifies the result from the comparing section, and outputs the amplified result to an output node pair, and a second positive feedback section which operates in synchronism with a second clock signal, and provides positive feedback to the output node pair.

Comparator and analog-to-digital converter

A plurality of analog signals are input to input terminals of an analog signal processing circuit ANAvia respective capacitors C. In a bias circuit Bias for supplying a bias voltage such as a signal ground of the analog signals to the analog signal processing circuit ANA, in an operational amplifier OpAS, a bias voltage VIr is input from a non-inverting input VIP of a built-in differentiate amplifier circuit, an output terminal of the built-in output amplifier circuit OAis connected to an inverting input terminal VIM of the differentiate amplifier circuit DA, and thereby a voltage follower is obtained. Furthermore, a plurality of output amplifier circuits OAthrough OAn are provided so that input terminals thereof are connected to output terminals of the differential amplifier circuit DA, and the output terminals are connected to input terminals INthrough INn of the analog signal processing circuit ANA

Bias circuit and semiconductor integrated circuit including the bias circuit

A comparator used in a parallel-type A/D converter, wherein a comparatorincludes reset transistors mra and mrb. When the comparatoris in the Reset state, the inverted signal /CLK of the clock signal is given to the PMOS reset transistors mra and mrb so as to forcibly reset both of the voltages at two internal nodes Va and Vb being a differential pair to a predetermined reset voltage by the reset transistors mra and mrb. The inverted signal /CLK of the clock signal is produced with a predetermined delay. Thus, when the comparatoris in the Reset state, the point in time at which to cancel the reset of the internal nodes Va and Vb is delayed from that at which the comparator performs a comparison operation. Therefore, even if the frequency of the clock signal and the frequency of the analog input signal are high, the voltages at the internal nodes forming a differential pair are well-balanced when the comparator is in the Reset state, thus improving the voltage comparison precision.

Comparator and A/D converter

A full-flash A/D converter, including a differential amplifier circuit row and a voltage comparison circuit row, has an adjusting circuitfor making the output dynamic range of differential amplifier circuits accurately fall within the input dynamic range of voltage comparison circuits. The adjusting circuitincludes a reference voltage generation circuitwhich has therein voltage generation circuitswhose resistors are connected in series. By this series connection, the area of the voltage generation circuitsis reduced, while the output dynamic range of the differential amplifier circuits Ato Am+1 in the differential amplifier circuit rowaccurately falls within the input dynamic range of the voltage comparison circuits Crto Crm+1 in the voltage comparison circuit rowFurthermore, half-circuits in the voltage generation circuitsare used to generate reference voltages, whereby the area of the voltage generation circuits is reduced further.

A/D converter

In an A/D converter, each preampincludes a preamp gain adjusting circuit. The preamp gain adjusting circuitsuppresses the gain of the preampand restricts a positive-negative output potential difference of the preamp only when the positive-negative output potential difference of the preampexceeds a reference potential. Accordingly, in the case where the frequency of an input signal to the A/D converter is high, even when the gain of the preamp is increased due to fabrication process variation, temperature variation or supply voltage variation, output strain of the preamp is minimally caused, and the characteristic degradation of the A/D converter can be suppressed.

When the performance of an A/D converter required by a system changes, power consumption of the overall system can be reduced. The resolution of an A/D converter is made variable by changing a current flowing through an amplifier by an external control signal that specifies the resolution. Thus, when the performance required by a system changes, it is possible to change the performance of the A/D converter and to prevent a performance overhead of the A/D converter. Consequently, power consumption of the A/D converter is reduced, and power consumption of the system as a whole is also reduced.

A/D converter, method of A/D conversion, and signal processing device

An A/D converter comprises a pipeline stage array in which plural pipeline stages are connected in series, each pipeline stage performing a pipeline operation on an inputted analog voltage to output a digital voltage; a number-of-bits control circuit for outputting a number-of-bits selection signal which indicates whether the operation of each pipeline stage should be carried out or halted, according to a number-of-bits control signal which indicates a resolution; and a correction circuit for compensating a digital value to be output, according to the number-of-bits control signal. Therefore, when resolution of the A/D converter, which is requested by the system, is changed, only the pipeline stages required for realizing the requested resolution are operated while the other pipeline stages are halted, whereby a reduction in power consumption of the A/D converter is realized and, simultaneously, a breakdown of an output from the A/D converter is avoided.

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Osaka, Japan

Junichi Naka