Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Other

Junichi Miyamoto

Koji Sakui

Yoshihisa Iwata

Nobuaki Ohtsuka

Shigeru Atsumi

Yasuo Itoh

Sumio Tanaka

Hiroaki Yoda

Takashi Mori

Tatsuya Kishi

Yoshiaki Asao

Keniti Imamiya

Minoru Amano

Tomomasa Ueda

Keiji Hosotani

Kenichi Imamiya

Naoto Tomita

Shinji Saito

Toshihiko Himeno

Kuniyoshi Yoshikawa

Jun-ichi Tsujimoto

Yumiko Iyama

Tomoharu Tanaka

Katsuya Okumura

Kenji Tsuchida

Seiichi Mori

Nobuo Hayasaka

Takeshi Kajiyama

Masaki Momodomi

Hironori Banba

Masao Kuriyama

Hisanori Aikawa

Ryousuke Takizawa

Hideko Oodaira

Kiyomi Naruke

Toshiharu Watanabe

Tetsuya Iizuka

Yoshihisa Sugiura

Naohiro Matsukawa

Kei Takano

Yasuhisa Takeyama

Kazuaki Ichinose

Shinji Saitoh

Noriaki Suzuki

Imamiya Keniti

A memory cell array has a unit formed from one memory cell and two select transistors sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data.

Nonvolatile semiconductor memory

A memory cell array has a unit formed from one memory cell and two select transistor sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one gate. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data.

A read circuit of a semiconductor memory according to the present invention is based on a self-reference sensing technique by which data stored in a memory cell is determined by first and second signals read out from a memory cell through first and second read operations. This read circuit includes a sense amplifier which determines the data stored in the memory cell based on a potential of an input node, a transfer transistor which is connected between the memory cell and the input node, a precharge circuit which sets the input node to a precharge potential, and a VBIAS generator which turns the transfer transistor cutoff based on the first signal.

Read circuit of semiconductor and read method using a self-reference sensing technique

A magnetic memory device includes a memory cell array including MTJ elements provided at the coordinates (x, y). First write lines extend in a direction neither perpendicular nor parallel to the magnetization easy axis direction of the MTJ elements. One and the other end of one first write line pass an upper or lower periphery of the memory cell array and a left or right periphery of the memory cell array, respectively. The first write lines and second write lines sandwich the MTJ elements. First write line drivers are connected to both ends of the first write lines, one and the other end of a pair of the first write line drivers connected to ends of one first write lines are located outside the upper or lower periphery and outside the left or right periphery, respectively. Second write line drivers are connected to both ends of the second write lines.

Magnetic memory device

A magnetic random access memory in which '0' data and '1' data are associated with resistance values of a non-magnetic layer of a magnetoresistive element, the resistance values being variable depending on orientation of magnetization of a magnetic free layer and a magnetic pinned layer which sandwich the non-magnetic layer, and current is let to flow to first and second write current paths, which are provided close to the magnetoresistive element and are separated from each other, thereby producing a composite write magnetic field, changing a direction of magnetization of the free layer, wherein the first write current path includes a channel region of an insulated-gate transistor that is disposed close to the free layer, and the transistor is controlled such that a channel current with a desired magnitude flows in the transistor.

Magnetic random access memory

A magnetic memory device includes first wiring which runs in the first direction, second wiring which runs in the second direction, a magneto-resistance element which is arranged at an intersection between the first and second wirings, a first yoke main body which covers at least either of the lower surface and two side surfaces of the first wring, a second yoke main body which covers at least either of the upper surface and two side surfaces of the second wiring, first and second yoke tips which are arranged on two sides of the magneto-resistance element in the first direction at an interval from the magneto-resistance element, and third and fourth yoke tips which are arranged on two sides of the magneto-resistance element in the second direction at an interval from the magneto-resistance element.

Magnetic memory device having yoke layer, and manufacturing method thereof

A write line is covered with a yoke material. The recording layer of an MTJ element is exchange-coupled to the yoke material. The total magnetic volume &#x3a3;Msi&#xd7;ti of the recording layer of the MTJ element and a portion of the yoke material that is exchange-coupled to the recording layer is smaller than the magnetic volume &#x3a3;Msi'&#xd7;ti&#x2032; of the remaining portion of the yoke material that covers the write line.

Magnetic memory device having yoke layer

Magnetic memory device having yoke layer, and manufacturing method

A read blocks are connected to a read bit line. The read block has MTJ elements connected in series or in parallel, or arranged by combining series and parallel connections between the read bit line and a ground terminal. The MTJ elements are stacked on a semiconductor substrate. The read bit line is arranged on the MTJ elements stacked. A write word line extending in the X-direction and a write bit line extending in the Y-direction are present near the MTJ elements in the read block.

Growing community of inventors

Yokohama, Japan

Junichi Miyamoto