Fujitsu Corporation

Fujitsu Semiconductor Limited

Junichi Mitani

Taiji Ema

Kenichi Watanabe

Makoto Yasuda

Shinichiroh Ikemasu

Kazuo Itabashi

Itsuo Yanagita

Kazushi Fujita

Toyoji Sawada

Masayoshi Asano

Michiari Kawano

Seiichi Suzuki

Tohru Anezaki

Satoshi Nakai

Kazuo Sukegawa

Takumi Hasegawa

Hiroshi Namba

Yoshimori Asai

A gate electrode, an element isolation film and a drain region in an LDMOS transistor formation region and a gate electrode, an element isolation film and an anode region in an ESD protection element formation region are formed to satisfy relationships of A&#x2267;Aand B&#x3c;Bwhere the LDMOS transistor formation region has an overlap length Aof the gate electrode and the element isolation film and a distance Bbetween the gate electrode and the drain region, and the ESD protection element formation region has an overlap length Aof the gate electrode and the element isolation film and a distance Bbetween the gate electrode and the anode region.

Semiconductor device and method of manufacturing the same

A semiconductor device has a first and a second active regions of a first conductivity type disposed on a semiconductor substrate, a third and a fourth active regions of a second conductivity type disposed on the semiconductor substrate, the second and the fourth active regions having sizes larger than those of the first and the third active regions respectively, a first electroconductive pattern disposed adjacent to the first active region and having a first width, a second electroconductive pattern disposed adjacent to the second active region and having a second width larger than the first width, a third electroconductive pattern disposed adjacent to the third active region and having a third width; and a fourth electroconductive pattern disposed adjacent to the fourth active region and having a fourth width smaller than the third width.

Semiconductor device

A manufacturing method of a semiconductor device comprises the steps of forming an etching stop insulating film () that covers at least side surfaces of a wiring () in a first region () and a first-stage conductive plug () in a second region (), then forming insulating films () on the etching stop insulating film () and the wiring (), then forming a hole () on a first-stage conductive plug () by etching a part of the insulating films () until the etching stop insulating film () is exposed, then exposing an upper surface of the first-stage conductive plug () by etching selectively the etching stop insulating film () through the hole (), and then forming a second-stage conductive plug () in the hole ().

The semiconductor device comprises a first conductive pattern, a second conductive patternformed adjacent to the first conductive pattern, a first conductor plugformed below a prescribed region of the first conductive pattern, a second conductor plugformed over a prescribed region of the first conductive pattern, a third conductor plugformed below a prescribed region of the second conductive pattern, which is adjacent to a prescribed region of the first conductive pattern, a fourth conductor plugformed over a prescribed region of the second conductive pattern, a third conductive patternformed above the first conductive patternand connected to the second conductor plug, and a fourth conductive patternformed above the second conductive patternand connected to the fourth conductor plug. The fourth conductor plugis arranged a position which is offset from the second conductor plug. The conductor plugsare offset each other in the longitudinal direction of the interconnections, whereby the parts of the interconnections having an increased width can be distanced from each other. Thus, the interconnections can be arranged at a small pitch without using an ArF exposure system and a half tone phase shift mask, which are expensive. Accordingly, the semiconductor device of high integration is provided at low costs while ensuring high fabrication yields.

The semiconductor device includes a MOSFET including a pair of impurity diffused regions formed on both sides of a gate formed on a semiconductor substrate; an insulation film covering a top of the MOSFET and having a through-hole opened on one of the impurity diffused regions formed in; and a capacitor formed at at least a part of an inside of the through-hole, the through-hole having a larger diameter inside than at a surface thereof or having a larger diameter at an intermediate part between the surface thereof and a bottom thereof than the surface and the bottom thereof.

Semiconductor device and method for fabricating the same

The semiconductor device according to the present invention comprises: a semiconductor substrate of a first conductivity type; a well of a second conductivity type different from the first conductivity type formed in a region surrounding a region of the semiconductor substrate ; a diffused layer of the second conductivity type formed, buried in the semiconductor substrate in the region and connected to the well on a side thereof; and a well of the first conductivity type formed in the semiconductor substrate in the region on the side of a surface thereof and electrically isolated from a rest region of the semiconductor substrate by the well and the diffused layer . This constitution of the semiconductor device permits the diffused layer and the well to be formed by the use of one and the same mask, whereby in electrically isolating the well from the semiconductor substrate by the well and the diffused layer , the triple well can be formed without increasing lithography steps.

Semiconductor device having triple well structure

The semiconductor device comprises a MOSFET including a pair of impurity diffused regions formed on both sides of a gate formed on a semiconductor substrate; an insulation film covering a top of the MOSFET and having a through-hole opened on one of the impurity diffused regions formed in; and a capacitor formed at least a part of an inside of the through-hole, the through-hole having a larger diameter inside than at a surface thereof or having a larger diameter at an intermediate part between the surface thereof and a bottom thereof than the surface and the bottom thereof.

The semiconductor device comprises a semiconductor substrate,of a first conduction-type, first wells,of a second conduction-type formed in a first region on the primary surface of the semiconductor substrate,, a second well,formed in a second region on the primary surface of the semiconductor substrate,other than the first region, a third well,of the first conduction-type formed in the first well, and high-concentration impurity-doped layers,of the first conduction-type formed in deep portions of the semiconductor substrate spaced from the primary surface of the semiconductor device in device regions. In the semiconductor device having triple wells according to the present invention, the high-concentration impurity-doped layers are formed in deep portions inside of the device regions. Accordingly, in the case where the wells have a low concentration so that the transistors have a low threshold voltage, the deep portions of the wells can independently have a high concentration. As a result, punch-through between the source/drain diffused layer of the transistor formed in the well in the well (double wells), and the well outside of the double wells can be prevented. This structure is also effective to prevent latch-up.

Semiconductor device and method for fabricating semiconductor device

The semiconductor device according to the present invention comprises: a semiconductor substrate,of a first conductivity type; a well,of a second conductivity type different from the first conductivity type formed in a region,surrounding a region,of the semiconductor substrate,; a diffused layer,of the second conductivity type formed, buried in the semiconductor substrate,in the region,and connected to the well,on a side thereof; and a well,of the first conductivity type formed in the semiconductor substrate,in the region,on the side of a surface thereof and electrically isolated from a rest region of the semiconductor substrate,by the well,and the diffused layer,. This constitution of the semiconductor device permits the diffused layer,and the well,to be formed by the use of one and the same mask, whereby in electrically isolating well,from the semiconductor substrate by the well,and the diffused layer,the triple well can be formed without increasing lithography steps.

Method for fabricating a semiconductor device

A semiconductor device including a semiconductor substrate 10 of a first conduction-type, first wells 20a, 20b of a second conduction-type formed in a first region on the primary surface of the semiconductor substrate 10, a second well 22a formed in a second region on the primary surface of the semiconductor substrate 10 other than the first region, a third well 22b of the first conduction-type formed in the first well, and high-concentration impurity-doped layers 26 of the first conduction-type formed in deep portions of the semiconductor substrate spaced from the primary surface of the semiconductor device in device regions. In a semiconductor device having triple wells, the high-concentration impurity-doped layers are formed in deep portions inside of the device regions. Accordingly, in the case where the wells have a low concentration so that the transistors have a low threshold voltage, the deep portions of the wells can independently have a high concentration. As a result, punch-through between the source/drain diffused layer of the transistor formed in an inner well of a double well, and the well outside of the double well can be prevented. This structure is also effective to prevent latch-up.

Growing community of inventors

Kawasaki, Japan

Junichi Mitani