Samsung Electronics Co., Ltd.

JunHyung Kim

Sungchul Park

Sanguhn Cha

Kiheung Kim

Ji-Hye Lee

Se Hee Han

Jonghyo Lee

Hyojin Jung

Jooyeol Lee

Kihyun Kim

Kijun Lee

Sunghye Cho

Myungkyu Lee

Kyung-Soo Ha

Sun Myung Choi

Sungrae Kim

Kyungsoo Ha

Minjun Kim

Ik-Joon Choi

Changyong Lee

Choi Sun

A semiconductor memory device includes n physical banks, each of which is configured to be entirely or partially included in one of a first logic bank or a second logic bank and arranged in a row direction, wherein n is an integer that is greater than or equal to 3, and wherein a proportion of a sum of respective widths of the n physical banks in the row direction to a height of the n physical banks in a column direction is a real number multiple that is not a multiple of 2.

Semiconductor memory device capable of expanding bank capacity adaptively to package size and method of designing the same

A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows. The scrubbing control circuit generates scrubbing addresses based on refresh operations performed on the memory cell array. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection operation on a plurality of sub-pages in a first memory cell row to count a number of error occurrences, and determines whether to correct a codeword in which an error is detected based on the number of error occurrences. An uncorrected or corrected codeword is written back, and a row address of the first memory cell row may be stored in the fault address register as a row fault address based on the number of error occurrences.

Semiconductor memory devices and methods of operating semiconductor memory devices

A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

A memory system includes a memory module having a plurality of memory devices therein. A memory controller is configured to transmit commands and addresses to the memory module in synchronization with a clock, input/output data to and from the memory module in synchronization with a data transfer clock, and perform system error correction operations on data read from the memory module. The plurality of memory devices perform on-die error correction operations, which are different from each other according to a physical location of the stored read data.

Memory systems having memory devices therein with enhanced error correction capability and methods of operating same

Electronic device with animated graphical user interface

Portable electronic device with animated graphical user interface

Growing community of inventors

Suwon-si, South Korea

JunHyung Kim