Shanghai Huali Microelectronics Corporation

Junhua Yan

Yi Ding

Jingxun Fang

Tong Lei

Minghua Zhang

A method of planarizing a polysilicon gate are provided, comprising: growing a polysilicon gate layer on a substrate with trenches; depositing an oxide layer on the polysilicon gate layer; oxidizing the top portion of the polysilicon gate layer from the flat surface of the oxide layer, so as to form a silicon oxide interlayer in the top portion of the polysilicon gate layer; the bottom of the silicon oxide interlayer is aligned with or lower than the low-lying areas of surface of the polysilicon gate layer; removing the oxide layer and the silicon oxide interlayer, so as to obtain a flat surface of the polysilicon gate layer and avoid a series of problems resulted from the uneven surface in the subsequent processes.

Method of planarizing polysilicon gate

A method of forming strained source and drain regions in a P-type FinFET structure is disclose. The method comprises depositing an isolation layer on the FinFET structure; applying a lithography and etching process to expose the isolation layer in two areas on opposite sides of the gate over the source/drain region of the FinFET, and etching through the exposed isolation layer to expose the semiconductive material of the source/drain region in the two areas; forming a recess in each of the source/drain region from the exposed semiconductive material; selectively epitaxially growing another semiconductive material in the recesses to increase the source/drain strain; and removing the rest of the isolation layer.

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Shanghai, China

Junhua Yan