Analog Devices,inc.

Columbia University

Analog Devices International Unlimited Company

Junhua Shen

Ronald Alan Kapusta

Peter R Kinget

Michael C W Coln

Alberto Marinas

Edward Chapin Guthrie

Mark D Maddox

Akira Shikata

Siwen Liang

Jayanth Kuppambatti

Jonathan Ephraim David Hurwitz

Michael Mueck

Hongxing Li

Nicolas Le Dortz

Erik D Barnes

Anping Liu

Daniel Peter Canniff

Sivanendra Selvanayagam

Doris Lin

Marlon Consuelo Maramba

Jonathan Hurwitz

Frank M Yaul

Jiannan Huang

Frank Yaul

Erik Barnes

Nicolas Ledortz

Provided herein are delay locked loops (DLLs) with calibration for external delay. In certain embodiments, a timing alignment system includes a DLL including a detector that generates a delay control signal based on comparing a reference clock signal to a feedback clock signal, and a controllable delay line configured to generate the feedback clock signal by delaying the reference clock signal based on the delay control signal. The timing alignment system further includes a delay compensation circuit that provides an adjustment to the controllable delay line to compensate for a delay of the feedback clock signal in reaching the detector.

Delay locked loops with calibration for external delay

A laser pulse emitter circuit comprises a laser diode and a laser diode driver circuit. The laser diode driver circuit includes an inductive circuit element in series with the laser diode, at least one capacitive circuit element connected in series with the inductive circuit element, and a switch circuit configured to activate the laser diode using duty cycling that includes an on-period and an off-period, wherein energy used in an activation of the laser diode is stored in the inductive circuit element and the at least one capacitive circuit element, and the stored energy is recycled by use in a subsequent activation of the laser diode.

Continuous wave laser driver with energy recycling

A time-of-flight (ToF) transmitter with self-stabilized optical output phase with minimal overhead is described, where the transmitter may either function as a slave in that the laser pulse phase and width can be controlled by the master ToF receiver, or it can function as a master where the laser control pulse is generated on the same chip or a companion chip. When the ToF transmitter functions as a slave and receives the laser pulse control signal, the techniques of this disclosure can transform the receive path and the pre-driver circuit into part of a delay locked loop (DLL).

Time of flight transmitter with self-stabilized optical output phase

A laser emitter circuit comprises a laser diode; a driver circuit configured to generate a drive signal; and a resonant circuit coupled to the driver circuit and the laser diode, wherein the resonant circuit is configured to use the drive signal of the driver circuit to generate a continuous wave sinusoidal drive signal to drive the laser diode.

Resonant laser driver

A current measurement circuit may use a probabilistic technique to determine a current from a circuit block. In one embodiment, the circuit includes a comparator circuit, a first current sensing element (such as a first resistor), and a control circuit. The first current sensing element is coupled to the comparator circuit to establish a first comparator input signal representative of the current at an input of the comparator circuit. The control circuit is coupled to the comparator circuit to obtain a first plurality of comparator output decisions corresponding to the first current sensing element for a specified count, determine a first proportion of comparator output decisions meeting a specified criterion, and determine a voltage value of the first comparator input signal from the first proportion. The control circuit is configured to determine a current value using the voltage value of the first comparator input signal and an impedance value of the first current sensing element. The current measurement circuit is relatively low-cost and easy to implement, without requiring a precision reference voltage, current, and/or high-cost analog-to-digital converters (ADCs).

Apparatus and method for current measurement

A successive-approximation-register analog-to-digital converter (SAR ADC) typically includes circuitry for implementing bit trials that converts an analog input to a digital output bit by bit. The circuitry for bit trials are usually weighted (e.g., binary weighted), and these bit weights are not always ideal. Calibration algorithms can calibrate or correct for non-ideal bit weights and usually prefer these bit weights to be signal-independent so that the bit weights can be measured and calibrated/corrected easily. Embodiments disclosed herein relate to a unique circuit design of an SAR ADC, where each bit capacitor or pair of bit capacitors (in a differential design) has a corresponding dedicated on-chip reference capacitor. The speed of the resulting ADC is fast due to the on-chip reference capacitors (offering fast reference settling times), while errors associated with non-ideal bit weights of the SAR ADC are signal-independent (can be easily measured and corrected/calibrated).

SAR ADCs with dedicated reference capacitor for each bit capacitor

A sampling circuit comprises a switch circuit and a gate bootstrapping circuit. The switch circuit includes a switch input to receive an input voltage, a gate input, and a switch output. The gate bootstrapping circuit provides a boosted clock signal to the gate input of the switch circuit. The boosted voltage of the boosted clock signal tracks the input voltage by a voltage offset. The gate bootstrapping circuit includes a single boost capacitance coupled between a first circuit node and a second circuit node. A high supply voltage is applied to the first circuit node and the input voltage is applied the second circuit node to generate the boosted voltage on the single boost capacitance.

Reconfigurable low power and low area gate bootsrapping circuit

A conversion time and an acquisition time of an ADC can be estimated so that a speed of the ADC can be calibrated. An ADC circuit can perform M bit-trials in its conversion phase and continue performing additional bit-trials in a calibration mode. The ADC can count the number of additional bit-trials performed, e.g., X bit-trials, that occur before the next conversion phase, where additional bit-trials can be considered to be the number of available bit-trials during an acquisition time if the ADC continues performing bit-trials instead of sampling an input signal. The ADC can estimate the conversion time and the acquisition time using M and X. Then, the conversion time of the ADC can be calibrated by adjusting one or more of the comparison time, DAC settling delay, and logic propagation delay.

Analog-to-digital converter speed calibration techniques

Improvements in analog-to-digital converter (ADC) circuit accuracy are described that can utilize a digital-to-analog converter (DAC) circuit with one or more redundant unit elements, or one or more bits redundancy or non-binary weighted capacitors, and can reuse the existing DAC circuit for noise reduction to save power and die area. An ADC circuit can use redundancy bit(s), e.g., one or more DAC unit elements of a main DAC, and the remaining lower bits of the main DAC for repeated bit trials, and can average the data from the repeated bit trials to suppress noise from conversions.

Analog-to-digital converter noise reduction techniques

A successive approximation register analog-to-digital converter (SAR ADC) typically includes circuitry for implementing bit trials that converts an analog input to a digital output bit by bit. The circuitry for bit trials are usually weighted (e.g., binary weighted), and these bit weights are not always ideal. Calibration algorithms can calibrate or correct for non-ideal bit weights and usually prefer these bit weights to be signal independent so that the bit weights can be measured and calibrated/corrected easily. Embodiments disclosed herein relate to a unique circuit design of an SAR ADC, where each bit capacitor or pair of bit capacitors (in a differential design) has a corresponding dedicated on-chip reference capacitor. The speed of the resulting ADC is fast due to the on-chip reference capacitors (offering fast reference settling times), while errors associated with non-ideal bit weights of the SAR ADC are signal independent (can be easily measured and corrected/calibrated).

A voltage sampling circuit is provided that may directly connect a non-zero power supply voltage VDD to switching circuits during input voltage sampling, setting a common mode voltage without using reference voltages produced by a reference voltage generator circuit, and without requiring a common mode buffer circuit. The voltage sampling circuit may be used in an operational amplifier input stage such as for a pipelined ADC circuit, or in a comparator circuit. A SAR ADC circuit is also provided, comprising a control circuit, the voltage sampling circuit, a capacitor array, and a comparator circuit for comparing outputs occurring from charge redistributions. The voltage sampling circuit may enable increased power efficiency, avoid leakage concerns, and increase maximum input voltage swing. Reference plate switches in the voltage sampling circuit may include gate-boosted devices or thicker-oxide I/O devices. The devices may include n-channel field-effect transistors or high threshold voltage p-channel field-effect transistors.

VDD-referenced sampling

Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage.

Systems and methods for providing a pipelined analog-to-digital converter

An analog-to-digital converter (ADC) system can sample an input voltage for at least a first conversion into a first N-bit digital value and to use the same input voltage sample for at least a second conversion into a second N-bit digital value. A difference between a result of the first conversion and a result of the second conversion can be driven toward zero to adjust weights of one or more of the bits to calibrated values for use in one or more subsequent analog-to-digital conversions of subsequent samples of the input voltage. Shuffling, dithering, or the like can help ensure that at least a portion of the decision paths used in the second conversion are different from the decision paths used in the first conversion. Calibration can be performed in the background while the the ADC is converting in a normal mode of operation.

ADC background calibration with dual conversions

An analog-to-digital converter (ADC) circuit comprises a digital-to-analog (DAC) circuit including at least N+n weighted circuit components, wherein N and n are positive integers greater than zero, and n is a number of repeat bits of the least significant bit (LSB) of the ADC circuit; a sampling circuit configured to sample an input voltage at an input to the ADC circuit and apply a sampled voltage to the weighted circuit components; a comparator circuit configured to compare an output voltage of the DAC to a specified threshold voltage during a bit trial; and logic circuitry configured to perform bit trials for the at least N+n weighted circuit components and adjust one or more parameters for one or more of N bit trials according to values of the n LSB repeat bits.

SAR ADC performance optimization with dynamic bit trial settings

Circuits and methods for implementing a residue amplifier are provided. In some embodiments, circuits for implementing a residue amplifier are provided, the circuits comprising: a first capacitor configured to be charged to an input voltage level and that discharges from the input voltage level to a reference voltage level; a comparator having a first input coupled to the first capacitor, a second input coupled to a reference voltage source, and an output that indicates when the charge on the first capacitor is above the reference voltage level; and a second capacitor configured to be charged to an output voltage based on the output of the comparator.

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Wilmington, MA, United States of America

Junhua Shen