Samsung Electronics Co., Ltd.

Seoul National University

Boston University

Junho Shin

Hongrak Son

Jungeun Park

Choongeun Lee

Youngsik Moon

Hanbyeul Na

Jongmin Kim

Jinyoung Kim

Jongmin Baek

Makoto Hirano

Dongmin Shin

Yongsung Cho

Jungho Ahn

Taehui Na

Wookrae Kim

Myungjun Lee

Geunyeong Yu

Youngjun Hwang

Sumin Kim

Bohwan Jun

Kangseok Lee

Jaehun Jang

Jiyoup Kim

Hyunseung Han

Seungbeom Park

Hao Wang

Hojun Lee

Lei Tian

Jangwoon Sung

Sangpyo Kim

Jiabei Zhu

Refrigerator

A substrate inspection apparatus includes a light irradiator including an objective lens and a plurality of optical fibers. The objective lens is configured to irradiate light to an illumination area on a semiconductor substrate having a plurality of circuit pattern layers, the plurality of optical fibers are adjacent a periphery of the objective lens and are configured to irradiate the light to a peripheral area adjacent the illumination area. A light generator is configured to generate the light. The light generator is configured to change an irradiation angle of the light to selectively irradiate the light to one or more of the objective lens and the plurality of optical fibers. A light analyzer is configured to obtain images of the circuit pattern layers from the light reflected from the illumination area and the peripheral area. The light analyzer is configured to model each of the circuit pattern layers of the semiconductor substrate to obtain image models and to measure an overlay between the circuit pattern layers through the images and the image models.

Substrate inspection apparatus and substrate inspection method

A method of transmitting data in a storage device includes encrypting original data based on a homomorphic encryption algorithm to generate encrypted data, generating a parameter for regeneration of a ciphertext higher than an operation level of the encrypted data by using the encrypted data and a key value, and transmitting the encrypted data and the parameter to an external host device.

Storage device, host device and data transfer method thereof

A method of operating a homomorphic encryption operation accelerator includes performing a number theoretic transform (NTT) operation on each of first homomorphic ciphertext and second homomorphic ciphertext, and performing a base conversion operation by adding a partial sum using a first value of the NTT operation.

Homomorphic encryption operation accelerator, and operating method of homomorphic encryption operation accelerator

A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.

Low density parity check decoder and storage device

A homomorphic operation accelerator includes a plurality of circuits and a homomorphic operation managing circuit. The plurality of circuits may perform homomorphic operations. The homomorphic operation managing circuit may receive cipher text data, homomorphic encryption information and homomorphic operation information from an external device. The homomorphic operation managing circuit may activate or deactivate each of a plurality of enable signals applied to the plurality of circuits based on the homomorphic encryption information and the homomorphic operation information. The homomorphic operation managing circuit may activate or deactivate each of the plurality of circuits based on the plurality of enable signals. The homomorphic encryption information may be associated with a homomorphic encryption algorithm used to generate the cipher text data. The homomorphic operation information may be associated with the homomorphic operations to be performed on the cipher text data.

Homomorphic operation accelerator and homomorphic operation performing device including the same

A resistive memory includes a memory cell array, a write/read circuitry and a control circuitry. The memory cell array includes a plurality of resistive memory cells coupled to a plurality of word-lines and a plurality of bit-lines. The write/read circuitry is coupled to the memory cell array through a row decoder and a column decoder, the write/read circuitry performs a write operation to write write data in a target page of the memory cell array, and verifies the write operation by comparing read data read from the target page with the write data. The control circuitry controls at least one of the row decoder, the column decoder and the write/read circuitry to control a resistance which a selected memory cell experiences according to a distance from an access point to the selected memory cell in the memory cell array based on an address.

Resistive memory devices and methods of operating resistive memory devices including adjustment of current path resistance of a selected memory cell in a resistive memory device

A memory device includes a memory cell array including memory cells disposed at points at which word lines and bit lines intersect, a first decoder circuit determining a selected bit line and non-selected bit lines among the bit lines, a second decoder circuit determining a selected word line and non-selected word lines among the word lines, a current compensation circuit providing a current path drawing a compensation current from the selected word line to compensate for off currents flowing in the non-selected bit lines, a first sense amplifier comparing a voltage of the selected word line with a reference voltage and outputting an enable signal, and a second sense amplifier outputting a voltage difference between the voltage of the selected word line and the reference voltage during an operating time determined by the enable signal in a readout operation mode of the memory device.

Memory device having an increased sensing margin

Growing community of inventors

Hwaseong-si, South Korea

Junho Shin