Samsung Electronics Co., Ltd.

Snu Rdb Foundation

Jungyun Choi

Jongwon Lee

Hyun Do Choi

Jeonghun Kim

Byungjune Choi

Se-Gon Roh

Minhyung Lee

Youn Baek Lee

Bonghyun Lee

Younbaek Lee

Jun Seomun

JeongHun Kim

Taewhan Kim

Hyoun Soo Park

Insub Shin

Kee Sup Kim

JongWon Lee

Kyounghwan Lim

Kyungtae Do

Chul Rim

Heechun Park

Yungjune Choi

Provided is a power transmitting device including an input side gear assembly that includes a single power input terminal and two power output terminals, an output side gear assembly that includes two power input terminals and a single power output terminal, the two power input terminals configured to operate using power received from the two power output terminals of the input side gear assembly, respectively, and a stopper module configured to block power to be transmitted through one of two power transmitting paths connecting the two power output terminals of the input side gear assembly and the two power input terminals of the output side gear assembly.

Power transmitting device, motion assistance apparatus, and method of controlling the motion assistance apparatus

A joint assembly may include a first rolling cam that includes a first cam portion, and a first extension extending from the first cam portion, and a second rolling cam that includes a second cam portion to be in contact with the first cam portion, and a second extension extending from the second cam portion.

Joint assembly and motion assistance apparatus including the same

Voltage monitors include a predelay cell having an input responsive to a first clock signal. This cell is configured to generate a predelayed clock signal at an output thereof. A serially-connected string of data delay cells is provided, which has an input responsive to the predelayed clock signal. A serially-connected string of clock delay cells is provided, which has an input responsive to a second clock signal that is synchronized to the first clock signal. A plurality latches are provided. The latches have respective data inputs, which are responsive to first periodic signals generated at respective outputs of the serially-connected string of data delay cells, and respective clock/sync terminals, which are responsive to second periodic signals generated at respective outputs of the serially-connected string of clock delay cells. The latches enable loading of a delay code value, which indicates power supply voltage variation.

Voltage monitor for generating delay codes

The integrated circuit includes first and second vias, a first buffer configured to receive a signal transmitted from the first via, a second buffer configured to receive a signal transmitted from the second via, a first detour circuit configured to receive a signal transmitted through the second buffer, a second detour circuit configured to receive a signal transmitted through the first buffer, a first selector configured to selectively output one of the signal transmitted from the first via and a signal transmitted through the first detour circuit, and a second selector configured to selectively output one of the signal transmitted from the second via and a signal transmitted through the second detour circuit. Each of the first and second buffers and the first and second detour circuits transmits a signal in only one direction.

Integrated circuit having main route and detour route for signal transmission and integrated circuit package including the same

Growing community of inventors

Suwon-si, South Korea

Jungyun Choi