International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Jungwook Yang

Hon-Sum Philip Wong

Sudhir Muniswamy Gowda

Hyun J Shin

Peter Hong Xiao

Viktor Ariel

John Peter Karidis

Daniel Michael Kuchta

Rama Nand Singh

Dale J Pearson

Eliyahu Shamsaev

Tibi Galambos

Zhong John Deng

An image capture system for mobile communications systems includes an imaging device for capturing optical image data and a data transfer apparatus coupled to a communications device communications device for transferring the optical image data to the communications device for transmittal over a communications network.

Image capture system for mobile communications

A single stack bipolar logic AND gate for low power applications comprising: a first differential pair of transistors, each transistor of the first differential pair having base, emitter and collector terminals, a base of a first transistor of the first differential pair receiving an input signal A and a base of the second transistor of the first differential pair receiving its complement signal {overscore (A)}, the emitters of each transistor of the first differential pair being connected at a common node to a first constant current source; a second differential pair of transistors, each transistor of the second differential pair having base, emitter and collector terminals, a base of a first transistor of the second differential pair receiving an input signal B and a base of the second transistor of the second differential pair receiving its complement signal {overscore (B)}, the emitters of each transistor of the second differential pair being connected at a common node to a second constant current source; and, a common voltage power supply source, the collector terminal of each first transistor of the first and second differential pairs being connected to the common voltage power supply source through a first resistance and defining a complement output node of the AND gate, and the collector terminal of each second transistor of the first and second differential pair being connected to the common voltage power supply source through a second resistance and additionally defining an output node of the AND gate, wherein the second resistance is greater than the first resistance.

Low voltage bipolar logic and gate device

A system and method of controlling the operation of linear variable-gain amplifiers to allow for such linear variable gain amplifiers to have a wider operating range at high current levels, control inputs for selectable gains and improved low-voltage operation. In a first mode, the amplifier includes an additional source of current to allow for an enhanced operating range. In a second embodiment, the amplifier includes a plurality of selective resistive levels and a selection system which allows the selection of one of the resistive levels which, in turn, controls the gain range of the amplifier system of the present invention. A third embodiment of the present invention illustrates the use of an amplifier system useful for a low voltage input signal to reduce errors caused by variations in the base to emitter in the two transistors providing the amplification. Also disclosed are embodiments for reducing the error in the amplifier output by providing additional stages to provide error reducing components which are added to the amplifier output.

Linear variable gain amplifiers

An analog-to-digital converter (ADC), including a plurality of first-level folded-differential-logic-encoders (FDLEs), coupled to receive an analog input signal and respective reference voltages and to provide respective outputs responsive to comparing a magnitude of the input signal to the respective reference voltages. The ADC has a second-level resultant FDLE, which is coupled to receive and combine the outputs of the first-level FDLEs to provide a digital value indicative of the magnitude of the input signal.

Differential interpolated analog to digital converter

In a current mode logic (CML) circuit, a high impedance state is implemented at the output for a bi-directional buffer. The output common mode voltage can be adjusted at the same time, which is particularly useful for a CML off-chip driver.

Current mode logic circuit with output common mode voltage and impedance control

A reference generator having a temperature-dependent output variation that is greater than an absolute temperature variation includes a first source and a second source, the first source generating a proportional to absolute temperature (PTAT) output. The second source generates an output having a temperature coefficient less than or equal to zero. The reference generator further includes a subtraction circuit coupled to the first and second sources, the subtraction circuit operatively subtracting the output of the second source from the PTAT output and generating an offset output, the offset output having a variation greater than an absolute temperature variation. Using the reference generator described herein in accordance with the invention, circuits having a relatively high temperature dependency can be easily compensated. Moreover, the reference generator is suitable for temperature sensing with large temperature dependency without requiring a high supply voltage.

Temperature-dependent reference generator

A circuit provides differential logic signals and includes a differential-input circuit having a first differential input and a second differential input. A first unit receives an input voltage signal and a supply voltage for providing a first voltage to the first differential input via a first node. A second unit receives the supply voltage for providing a second voltage to the second differential input via a second node. The differential-input circuit outputs a signal in accordance with the first and second voltages.

Differential-input circuit

A driver circuit having a minimized and/or controllable output common mode voltage comprises a differential amplifier having, a passive element as a biasing source for establishing a bias current in the differential amplifier and a control amplifier operatively coupled to the differential amplifier in a feedback arrangement, the control amplifier generating a control signal. The differential amplifier is responsive to the control signal for providing a voltage at an output of the driver circuit that is substantially independent of an input signal presented to an input of the driver circuit. By eliminating the need for an active device (e.g., transistor) as a bias current source, the output common mode voltage of the driver circuit is minimized. A reference signal coupled to the control amplifier, in conjunction with the feedback arrangement, substantially fixes the output common mode voltage of the driver circuit to a predetermined value.

Driver circuit with output common mode voltage control

An encoding circuit for use with a comparator, includes a plurality of logic elements for receiving an input from a comparator, and a Gray code encoder for receiving an output from the plurality of logic elements. Both first and second type comparator errors (e.g., meta-stability errors and bubble-errors) are substantially eliminated simultaneously by the logic elements.

Bubble and meta-stability error immune gray-code encoder for high-speed A/D converters

Disclosed is an image sensor including one or more dummy pixels that produce a reference signal which is used to compensate for errors within the devices of the main pixel cells. In one embodiment, at least one dummy pixel is used in conjunction with other circuitry to correct for nonlinearities in the transfer characteristic of a source follower transistor within each pixel. In another embodiment, an array of dummy pixels is used to correct for leakage current within the pixels during an electronic shutter mode of operation. The two techniques can be combined whereby both threshold voltage mismatch and leakage current are compensated for.

Image sensor with dummy pixel or dummy pixel array

The present invention relates to an automatic gain control circuit in which the automatic gain control function is performed entirely in the digital domain. In an illustrative embodiment, the digital automatic gain control circuit for an image sensor having associated therewith an analog-to digital (A/D) converter for converting analog electrical signals from the image sensor to corresponding digital codes, includes a min/max detector for determining minimum and maximum electrical signal values from the digital codes of the A/D converter for each frame of image. A filter coupled to the min/max detector dampens instantaneous changes of the minimum and maximum values by filtering to provide filtered minimum and maximum values. A digital-to-analog (D/A) converter coupled to the filter generates minimum and maximum analog reference voltages corresponding to the respective minimum and maximum filtered values, the reference voltages being applied to the A/D converter to control associated amplitudes of the digital codes provided thereby.

Digital automatic gain control circuit for image system

A CMOS image sensor is provided in which correlated double sampling is performed entirely in the digital domain. In an exemplary embodiment, the image sensor includes a plurality of imager cells arranged in rows and columns, where the imager cells of a particular column are coupled to a column data line of that column. Each active imager cell is capable of selectively providing a first output on an associated column data line indicative of a reset level during a first sampling interval. During a second sampling interval, each active imager cell provides a signal output on the associated column data line indicative of an amount of light incident upon that imager cell. At least one analog to digital (A/D) converter is coupled to the column data lines and converts the first and signal outputs on each column data line to first and second digital codes, respectively, to complete a correlated double sampling operation. The invention eliminates the need for analog capacitors to store the reset and signal levels.

Image sensor with direct digital correlated sampling

A circuit for interfacing CMOS logic devices, having an output level range associated therewith, with MESFET logic devices, having an input level range associated therewith, comprises a depletion mode MESFET device, coupled between at least one CMOS device and at least one other MESFET device, the depletion mode MESFET device limiting a current through a gate-source junction thereof such that the output level range of the at least one CMOS device is altered to be compatible with the input level range of the at least one other MESFET device. Another circuit for interfacing CMOS logic devices, having an output level range associated therewith, with MESFET logic devices, having an input level range associated therewith, comprises: a source follower MESFET device coupled to an output terminal of at least one CMOS device; a first depletion mode MESFET device, coupled to the source follower MESFET device, the first depletion mode MESFET device limiting a current through a gate-source juction thereof such that the output level range of the at least one CMOS device is altered to be compatible with the input level range of at least one other MESFET device; and a second depletion mode MESFET device, coupled to the first depletion mode MESFET device, for providing a discharge path; wherein an input terminal of the at least one other MESFET device is coupled between the first and second depletion mode MESFET devices.

Circuit for interfacing a first type of logic circuit with a second type

A bias circuit for a flash A/D converter having a first bus line and a second bus line includes a voltage reference operatively coupled to an operational amplifier circuit. The bias circuit further includes a first transistor, a second transistor, a first load resistor and a second load resistor. The collectors of the first transistor and second transistor are coupled to a supply voltage source through the first load resistor and second load resistor, respectively. The emitters of the first and second transistors are coupled to the first and second bus lines respectively. One of the first and second bus lines is coupled to the operational amplifier, providing a signal for negative feedback. A first current bypass circuit is coupled from the supply voltage source to the first bus line and provides a first current which is substantially equal to the quiescent current of the first bus line. A second current bypass circuit is coupled from the supply voltage source to the second bus line and provides a second current. The second current is less than the quiescent current of the second bus line by a magnitude substantially equal to the load current of one comparator attached to the bus lines. The voltage on the first bus line and second bus line are substantially equal and substantially constant. A differential voltage is developed across the collectors of the first transistor and the second transistor which is responsive to a change in current in the first and second bus lines.

Growing community of inventors

West Nyack, NY, United States of America

Jungwook Yang