Infineon Technologies Ag

Infineon Technologies North America Corp.

Jungwon Suh

Alessandro Minzoni

Jong-Hoon Oh

Jung Pill Kim

Woo-Tag Kang

A clock stop detector for a memory comprises a first switch that closes in response to a first logic level of a clock signal to charge a capacitor, a second switch that closes in response to a second logic level of the clock signal to discharge the capacitor, and a logic circuit that outputs a control signal based on an inverted clock signal and a charge on the capacitor.

Clock stop detector

A circuit including a deskew circuit. The deskew circuit is configured to receive a first signal having a first edge delayed from a second edge of a second signal by a first delay and a third edge delayed from a fourth edge of the second signal by a second delay. The deskew circuit is configured to provide a third signal having a first deskewed edge delayed from the first edge by a third delay and a second deskewed edge delayed from the third edge by a fourth delay. The difference between the fourth delay and the third delay is substantially equal to the difference between the first delay and the second delay.

Circuit including a deskew circuit for asymmetrically delaying rising and falling edges

A data bus structure for a dynamic random access memory (DRAM) according to the present invention includes a series of data buses, each shared by a plurality of memory banks, and a switching device to selectively couple the data buses to a global data bus to enable the memory device to provide and receive data. The data bus structure conserves space on a chip or die and prevents significant timing skews for data accessed from different memory banks.

Memory data bus structure and method of transferring information with plural memory banks

A method of performing a self refresh of memory cells in a memory device. The memory device includes a first group of cell blocks and a second group of cell blocks and each cell block of the first group shares at least one sense amplifier with a cell block of the second group. The method includes simultaneously activating each cell block of the first group. While the cell blocks of the first group are activated, each memory cell in the first group is refreshed. The method further includes simultaneously activating each cell block of the second group. While the cell blocks of the second group are activated each memory cell in the second group is refreshed.

Memory device having low Vpp current consumption

A dynamic random access memory (DRAM) cell structure (and method for making a DRAM cell structure) that is more suitable than current DRAM structures for implementation in ever decreasing semiconductor fabrication geometries. The DRAM cell structure comprises a deep trench (DT) capacitor formed in a substrate. A recess is formed in the substrate proximate the deep trench capacitor. A gate is formed that extends into the recess but does not completely occupy the recess. A source is formed in the substrate in a region beneath the recess. A drain is formed in the substrate in a region laterally and vertically offset from the source. A channel between the source and drain is created beneath the gate along a side wall of the recess. Thus, the depth of the recess determines the length of the channel region. With this DRAM cell structure, it is easier to avoid the high doping concentration issue and the short channel effect. Consequently, this DRAM cell structure can be employed with smaller fabrication technologies.

Partially recessed DRAM cell structure

A bit line sensing scheme is provided for a semiconductor memory device that significantly reduces current drain during a self-refresh mode. After bit line sensing of a selected wordline and deactivation of the selected wordline, a capacitor is connected to a source node associated with a bit line sensing amplifier for the selected wordline to charge the capacitor with charge remaining on the bit line. Then, during the next activate-precharge cycle for another selected wordline, the capacitor is coupled to the source node of a bit line sensing amplifier associated with another selected wordline to discharge charge stored by the capacitor to the bit line associated with said other selected wordline. Thus, charge is returned from the bit line to the capacitor. This is where the self-refresh current reduction is achieved.

Sensing current recycling method during self-refresh

Twin-cell bit line sensing structures and techniques are provided. Utilizing a folded bit line like structure, with bit line and complementary bit lines located together, sense amplifiers can be between cell arrays. Bit line switches, responsive to activated word lines in an array, may be used to selectively couple bit line pairs of the shared arrays with the sense amplifiers with a single word line activation.

Twin-cell bit line sensing configuration

A dynamic random access memory device is capable of converting from a full density memory device to a reduced density memory device. The reduced density memory device compensates for cell failures in a plurality of cell blocks, regardless of the location of the cell failures. The memory device includes a row address mapping fuse for selectively determining row address combinations capable of storing data bits. A row address mapping logic is coupled to the row address mapping fuse and is capable of routing data bits to the address combinations capable of storing data bits.

Memory device with a flexible reduced density option

Methods and circuits for minimizing or eliminating the effect of trimming circuits in a voltage generating circuit are provided. In general, the effects of channel resistance of switches of the trimming circuit are reduced by utilizing switches in series with the output, rather than in parallel with resistors, as in conventional trimming circuits. Because the switches are not in parallel with the resistors, when the switches are turned on, no channel resistance is added to the effective resistance controlled by the trimming circuit.

Voltage trimming circuit

The present invention relates to a memory cell having a quasi-folded bit line sensing arrangement with an open bit line cell array. The memory cell array noise is negligible compared to the conventional open bit line. Also, the twisted bit line structure can be applied for the invention to reduce the inter-bit line coupling noise. The embodiments of the present invention reduce the size of the edge array, reduce the sensing power requirements, and provide a simple bit line layout. According to one embodiment of the present invention, a memory device comprises a plurality of sense amplifiers, each sense amplifier enabling access to data associated with arrays of cells; a bit line pair being coupled to each sense amplifier and comprising a bit line and a complementary bit line; a plurality of word lines associated with an array of cells; and a plurality of switches is employed to enable access to memory cells of the memory device. The arrangement of the memory device enables a VBLEQ signal to be coupled directly to the bit lines and complementary bit lines of the memory device. An improved sense amplifier having precharge circuit of a single transistor is also described. According to another aspect of the present invention, a method of reading and writing data in a memory device is described. The method comprises providing a bit line pair having a bit line and a complementary bit line, and coupling the bit line pair to a plurality of sense amplifiers. A plurality of switches is also provided in the bit line pair. The plurality of switches enables access to a memory cell to enable reading and writing data in the memory cell.

Memory device and method of reading data from a memory cell

A circuit to operate a semiconductor integrated circuit memory device having memory cells in a deep power down mode. The power down circuit includes a transistor switch connected between an external voltage source and the device memory cells and peripheral circuits, a generator for providing a control voltage of a first level different from the value of the external voltage, and a multiplexer that receives as one input the control voltage and as a second input the external voltage. The multiplexer has a selected output of one of the control voltage and external voltage that is applied to a control electrode of the transistor switch. When deep power down mode operation is required, the multiplexer responds to a power down control flag signal to apply the external voltage to the transistor control electrode to turn off the transistor and block application of the external voltage to the memory cells and peripheral circuits. In normal operation, no power down control flag signal is produced and the multiplexer applies the control voltage of a first level to the transistor switch control electrode to cause the transistor to conduct and apply the external voltage to the device memory cells and peripheral circuits for normal operation.

Deep power down switch for memory device

A voltage down converter for a semiconductor memory device to convert an external voltage to a lower value internal voltage for the device, has a voltage generator that produces a reference voltage corresponding to the value of the internal voltage, a comparator having opposite polarity inputs for producing an amplified output control signal, and a pull-up device operating from the external voltage that receives the control signal from the comparator to produce the internal voltage as an input. A dual source follower is located between the reference voltage generator and comparator and has two sections having cross-coupled inputs which respectively receive the internal reference voltage and the internal voltage to produce output voltages moving in opposite directions, each of which is applied to one input of the comparator, thereby translating the difference between Vintref and Vint to a level in a range that can be better amplified by the comparator.

Voltage down converter for low voltage operation

A memory comprising 2dynamic random access memory (DRAM) banks, wherein n is an integer greater than or equal to 2, 2refresh row address counter circuits configured to generate 2sets of refresh row address signals in response to 2refresh enable signals, a multiplexer circuit configured to provide the 2sets of refresh row address signals to the 2DRAM banks in response to the 2refresh enable signals, and a bank select circuit configured to provide 2bank enable signals to the 2DRAM banks in response to at least (n+1) external address signals and in response to the 2refresh enable signals is provided. The 2bank enable signals cause at least two but less than all of the 2DRAM banks to be refreshed using at least two of the 2sets of refresh row address signals in response to the 2refresh enable signals.

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Apex, NC, United States of America

Jungwon Suh