Arm Limited

Micron Technology Incorporated

Integrated Silicon Solution Incorporated

Ovonyx Memory Technology, LLC

Jungtae Kwon

David Kim

Sunil Bhardwaj

Pierre C Fazan

Michael Allen Van Buskirk

Fakhruddin Ali Bohra

Shri Sagar Dwivedi

Viktor Koldiaev

Vivek Nautiyal

Young Suk Kim

Christian Caillat

Satinderjit Singh

Yew Keong Chong

Andy Wangkun Chen

Bo Zheng

Gus Wai-Yan Yeung

Lalit Gupta

Pranay Prabhat

Nicolaas Klarinus Johannes Van Winkelhoff

Anurag Mittal

Jitendra Dasani

Hemangi Umakant Gajjewar

Cezary Pietrzyk

Abhishek B Akkur

Moon-Hae Son

Ingming Chang

Manoj Puthan Purayil

Various implementations described herein refer to an integrated circuit having a memory cell array with a first number of rows and a second number of rows. The integrated circuit may include a first pre-decoder that receives a row address and selects a first row from the first number of rows based on the row address. The integrated circuit may include a second pre-decoder that receives the row address from the first pre-decoder and selects a second row from the second number of rows based on the row address received from the first pre-decoder. The integrated circuit may include a single row decoder that receives the row address and selects either the first row or the second row based on a row selection bit from the row address.

Wordline decoder circuitry

Various implementations described herein are directed to an integrated circuit having multiple banks of memory cells and a local input/output (IO) component for each bank of the multiple banks. The integrated circuit may include multiple signal lines that are coupled to the multiple banks with the local IO components. At least one signal line of the multiple signal lines is wider than one or more of the other signal lines.

Routing structures for memory applications

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a memory bank having an array of memory cells that are accessible via a selected wordline and a pair of complementary bitlines. The integrated circuit may include a dummy wordline coupled to each of the pair of complementary bitlines via a pair of coupling capacitors. The dummy wordline may mimic the selected wordline. During transitions of the pair of complementary bitlines between first and second logic states, the dummy wordline may receive coupling capacitance from the pair of complementary bitlines via the pair of coupling capacitors.

Tracking wordline behavior

Various implementations described herein are directed to an integrated circuit having a memory cell array with multiple rows of memory cells including at least one redundant row of memory cells. The memory cell array may be partitioned into multiple regions of memory cells including a first region of memory cells corresponding to a first part of the redundant row of memory cells and a second region of memory cells corresponding to a second part of the redundant row of memory cells. The integrated circuit may include wordline driver circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells. In some instances, the integrated circuit may include row shift circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells.

Redundancy schemes for memory cell repair

Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment.

Techniques for reducing disturbance in a semiconductor memory device

Techniques for providing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation, a second region connected to a bit line extending a second orientation, and a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.

Techniques for providing a semiconductor memory device

A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells.

Memory device and method of operation of such a memory device

A semiconductor memory device is disclosed. In one particular exemplary embodiment, the semiconductor memory device includes a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation. Each memory cell may also include a second region connected to a bit line extending a second orientation. Each memory cell may further include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation and a second barrier wall extending in the second orientation and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.

Semiconductor memory device

Techniques for reducing disturbance in a semiconductor device

A system, method and computer program product are provided for producing an instance of a memory device from a banked memory architecture. The banked memory architecture specifies a maximum number of memory banks and a maximum number of rows per memory bank. The method comprises the step of receiving input parameters indicating a number of properties of the memory device, the properties comprising at least a number of rows R for the memory device. Thereafter, a degeneration process is performed on the banked memory architecture in order to produce the instance of a memory device having those properties. The degeneration process comprises the steps of: (i) selecting a number of memory banks B for the instance, where the number is an integer less than or equal to the maximum number of memory banks specified by the banked memory architecture, and B is not constrained to be a factor of R; and (ii) partitioning the number of rows R amongst the selected memory banks such that in each memory bank the number of rows in that memory bank is an integer less than or equal to the maximum number of rows per memory bank specified by the banked memory architecture. This has been found to provide a very flexible technique for producing instances from a banked memory architecture allowing fine granularity in the number of rows provided, which is particularly suitable for highly banked memory architectures.

Degeneration technique for designing memory devices

A memory arrayhas an address decoderresponsive to a repair signal to operate either in a normal mode or a repair mode. In the normal mode a data bit is stored within a single memory cell. In the repair mode a data bit is stored within multiple memory cellsof a common column of memory cells sharing bit lines. This provides increased defect resistance when operating in the repair mode at the cost of reduced memory capacity.

Repairing integrated circuit memory arrays

A pulse delay circuit that provides a delay for a pulsed input signal that does not vary significantly under changing temperature, power supply voltage or process conditions. The delay provided by the pulse delay circuit is not significantly limited in duration. The pulse delay circuit includes a pulse detector, an RC delay circuit and a pulsed signal generator. The delay is primarily determined by the RC time constant of the RC delay circuit.

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San Jose, CA, United States of America

Jungtae Kwon