Samsung Electronics Co., Ltd.

Jungoo Kang

Gihee Cho

Sanghyuck Ahn

Hyun-Suk Lee

Hyunsuk Lee

Sangyeol Kang

Jin-Su Lee

Hongsik Chae

Jiwoon Park

Taekyun Kim

Jinsu Lee

Provided is a semiconductor device. The semiconductor device includes a lower structure; a lower electrode on the lower structure; a dielectric layer on the lower electrode; and an upper electrode on the dielectric layer, wherein the lower electrode includes a bending reducing layer and a dielectric constant-increasing layer between the bending reducing layer and the dielectric layer, the dielectric constant-increasing layer is configured to increase a dielectric constant of the dielectric layer, and an elastic modulus of the bending reducing layer is greater than an elastic modulus of the dielectric constant-increasing layer.

Semiconductor device and method of manufacturing the same

A semiconductor memory device includes a capacitor having a bottom electrode and a top electrode, a dielectric layer between the bottom and top electrodes, and an interface layer between the top electrode and the dielectric layer, the interface layer including a metal oxide and an additional constituent at a grain boundary of the interface layer.

Method of fabricating a semiconductor memory device

Semiconductor devices including a capacitor and methods of forming the same are provided. The semiconductor devices may include a capacitor that include a lower electrode, an upper electrode on the lower electrode, and a dielectric layer extending between the lower electrode and the upper electrode. The lower electrode may include a doped region that contacts the dielectric layer, and the doped region of the lower electrode is configured to increase a capacitance of the capacitor.

Semiconductor devices including capacitor and methods of manufacturing the semiconductor devices

An integrated circuit device includes a capacitor structure, wherein the capacitor structure includes: a bottom electrode over a substrate; a supporter on a sidewall of the bottom electrode; a dielectric layer on the bottom electrode and the supporter; and a top electrode on the dielectric layer and covering the bottom electrode. The bottom electrode comprises: a base electrode layer over the substrate and extending in a first direction that is perpendicular to a top surface of the substrate, and a conductive capping layer including niobium nitride that is between a sidewall of the base electrode layer and the dielectric layer, and also between a top surface of the base electrode layer and the dielectric layer.

Integrated circuit devices and methods of manufacturing the same

A method of manufacturing a semiconductor device includes: forming electrode holes by etching a mold structure including a mold layer and a support layer which are stacked on a substrate; forming lower electrode pillars filling the electrode holes; etching a portion of the support layer between the lower electrode pillars to form a support pattern having a through-hole exposing a portion of a top surface of the mold layer; removing the mold layer through the through-hole to expose sidewalls of the lower electrode pillars; and selectively forming lower electrode patterns on the sidewalls and top surfaces of the lower electrode pillars.

Semiconductor devices including a support pattern on a lower electrode structure

A semiconductor device includes; a bottom electrode on a substrate, a supporting pattern between the bottom electrode and an adjacent bottom electrode, a top electrode covering the bottom electrode and the supporting pattern, and a dielectric layer between the bottom electrode and the top electrode and between the supporting pattern and the top electrode. The bottom electrode may include a first portion including a seam and a second portion on the first portion, a top end of the second portion may be disposed at a height lower than an upper surface of the supporting pattern, and a portion of a bottom end of the second portion may be exposed to the seam.

Semiconductor device

A semiconductor device and a method of manufacturing the same, the device including a plurality of lower electrodes on a semiconductor substrate; a support pattern connecting the lower electrodes at sides of the lower electrodes; and a dielectric layer covering the lower electrodes and the support pattern, wherein each of the plurality of lower electrodes includes a pillar portion extending in a vertical direction perpendicular to a top surface of the semiconductor substrate; and a protrusion protruding from a sidewall of the pillar portion so as to be in contact with the support pattern, the pillar portion includes a conductive material, the protrusion includes a same conductive material as the pillar portion and is further doped with impurities.

Semiconductor devices are provided. A semiconductor device includes a first portion of a lower electrode structure on a substrate. The semiconductor device includes a first support pattern being in contact with a first portion of a sidewall of the first portion of the lower electrode structure. The semiconductor device includes a second portion of the lower electrode structure on a second portion of the sidewall of the first portion of the lower electrode structure. The semiconductor device includes an upper electrode on the second portion of the lower electrode structure and on the first support pattern. Moreover, the semiconductor device includes a dielectric layer between the upper electrode and the second portion of the lower electrode structure.

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Seoul, South Korea

Jungoo Kang