Boe Technology Group Co., Ltd.

Jungmok Jun

Xue Dong

Guangliang Shang

Xing Yao

Seungwoo Han

Haoliang Zheng

Yunsik Im

Mingfu Han

Hyunsic Choi

Ming Jin Chen

Yuanbo Zhang

Yujie Gao

Yinglong Huang

Disclosed is a shift register unit, a gate driving circuit and a driving method, as well as a display apparatus. The shift register unit has a working cycle including an input phase, an output phase, a reset phase and a maintaining phase. In the reset phase, a clock signal is transmitted to an output terminal to pull a voltage of the output terminal down to a reference voltage, and the pulled-down voltage of the output terminal is subsequently changed from the reference voltage to a gate-off voltage. In the maintaining phase, the voltage of the output terminal is maintained at the gate-off voltage. The reference voltage is smaller than the gate-off voltage.

Shift register unit, gate driving circuit and driving method thereof, and display apparatus

The present disclosure provides a shift register, including: an input unit, an output control unit, a first pull-down unit, a second pull-down unit, a reset unit, and a pull-down control unit. The input unit comprises a control terminal connected to a signal input terminal, a first terminal connected to a first voltage terminal, and a second terminal connected to a first node. The output control unit comprises a control terminal connected to the first node, a first terminal connected to a first clock signal terminal, and a second terminal connected to a signal output terminal. The first pull-down unit comprises a control terminal connected to a second node, a first terminal connected to the first node, and a second terminal connected to a compensation signal terminal. The second pull-down unit comprises a control terminal connected to the compensation signal terminal, and a first terminal connected to the second node.

Shift register, GOA circuit containing the same, and related display device

The present disclosure provides a shift register circuit, an array substrate, and a display device. For a first driver and a second driver adjacent to each other in a direction substantially perpendicular to the gate line, a first driving input wiring of the first driver is arranged to input a first clock driving signal to individual shift registers successively from a shift register at a first end position of the first driver to a shift register at a second end position of the first driver, and a second driving input wiring of the second driver is arranged to input a second clock driving signal to individual shift registers successively from a shift register at a second end position of the second driver to a shift register at a first end position of the second driver.

Shift register circuit, array substrate and display device

The present application discloses a method of driving a gate driving circuit in an operation cycle divided into a first sub-cycle and a second sub-cycle, including providing a gate driving circuit having a first plurality of shift register units with a second plurality of shift register units, the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal CLK/CLK, a second bias-control terminal to receive a second/first bias signal CLK/CLK, and a first control level terminal provided with a first control voltage VC, the second plurality of shift register units being configured so that each odd/even numbered shift register unit includes a third bias-control terminal to receive a third/fourth bias signal CLK/CLK, a fourth bias-control terminal to receive a fourth/third bias signal CLK/CLK, and a second control level terminal provided with a second control voltage VC; configuring the first bias signal CLKand the second bias signal CLKas first pair of clock signals at respective turn-on level and turn-off level with inverted phase in the first sub-cycle; setting the first control voltage VCto a turn-off level so that the first plurality of shift register units is controlled along with the first pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the first sub-cycle; setting both the third bias signal CLKand the fourth bias signal CLKto a turn-off level and the second control voltage VCto turn-on level during the first sub-cycle; configuring the third bias signal CLKand the fourth bias signal CLKas second pair of clock signals at respective turn-on level and turn-off level with inverted phase in the second sub-cycle; setting the second control voltage VCto a turn-off level so that the second plurality of shift register units are controlled along with the second pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the second sub-cycle; and setting the first bias signal CLKand the second bias signal CLKto a turn-off level and the second control voltage VCto a turn-on level during the second sub-cycle.

Shift register unit, gate driving circuit and driving method, and display apparatus

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Beijing, China

Jungmok Jun