Samsung Electronics Co., Ltd.

Jungmin You

Seongjin Cho

Hoyoun Kim

Wonhyung Song

Hijung Kim

A memory device including: a memory cell array including memory cell rows; and a control logic circuit to perform a row, write, read, or pre-charge operation on the memory cell rows in response to an active, write, read, or pre-charge command, wherein the control logic circuit is further configured to: calculate a first count value by counting the active command and a second count value by counting the write command or the read command, with respect to a first memory cell row, during a row hammer monitor time frame; determine a type of row hammer of the first memory cell row based on a ratio of the first count value to the second count value; and adjust a pre-charge preparation time between an active operation and the pre-charge operation, by changing a pre-charge operation time point according to the determined type of row hammer.

Method of controlling row hammer and a memory device

Provided are a method for controlling a row hammer and a memory device. The memory device includes: a memory cell array having memory cell rows; a control logic circuit configured to classify access addresses of the memory cell array as real and fake entries, and identify a row hammer address from among the access addresses; and a refresh control circuit configured to refresh a memory cell row physically adjacent to a memory cell row indicated by the row hammer address during a row hammer monitoring time frame. The control logic circuit is further configured to promote a fake entry to a real entry based on the number of accesses of the fake entry being equal to or greater than a first threshold.

Memory device and method for controlling row hammer

Provided are a memory device for detecting a weakness of an operation pattern and a method of operating the same. The method includes: storing address information and activation count information regarding N word lines from among the plurality of word lines in a register including N entries; based on activation of a first word line different from the N word lines, storing address information and activation count information regarding the first word line in an entry from which information is evicted from among the N entries; and generating first weakness information based on a number of evictions performed on the register during a first period.

Memory device detecting weakness of operation pattern and method of operating the same

A memory device includes a memory cell array having a plurality of memory cells connected to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation on at least one of target rows of the memory cell array in response to a refresh management mode command, a weak pattern detector that is activated according to a register update bit value included in the refresh management mode command and that outputs a risk level for each of the target rows, and a mode register circuit that updates at least one mode register value according to the risk level.

Memory device, memory system having the same and method of operating the same

A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a target row refresh logic circuit configured to select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values, and perform a refresh operation on first memory cells of the plurality of memory cells connected to a wordline of the plurality of wordlines indicated by the refresh row address, a victim point table configured to store the victim point values for the target row addresses, and a victim point accumulator configured to receive a first row address from an external device, and accumulate a first victim point value for at least one target row address corresponding to the first row address during a unit time period.

Memory device, memory system having the same and operating method thereof

The present disclosure provides methods, apparatuses, and systems having reduced power noise in a refresh operation. In some embodiments, an operating method includes: performing, in response to receiving a first refresh command, a first normal refresh, at a first refresh timing, in which first N word lines of a plurality of word lines are simultaneously refreshed, and a first target refresh, at a second refresh timing, on at least one first victim word line that is adjacent to a maximum activated word line that is most frequently activated from among the plurality of word lines; and performing, in response to receiving a second refresh command, a second normal refresh, at a third refresh timing, in which second N word lines are simultaneously refreshed, and a second target refresh, at a fourth refresh timing, on at least one second victim word line that is adjacent to the maximum activated word line.

Memory device having reduced power noise in refresh operation and operating method thereof

A method of controlling a row hammer swaps a first address entry with a second address entry having the smallest second access number and randomly swaps the first address entry with a third address entry having a third access number which is not the greatest value, in an address table representing a correlation between an address entry accessed during a row hammer monitoring time frame and an access number, thereby preventing a hacker-pattern row hammer aggression from being easily performed.

Memory device and method of controlling row hammer

A row hammer preventing circuitry including: a first table storing a count value representing a hit count and an address bit of multiple entries, each entry corresponding to access-requested target rows; a second table including safe bits and a safe bit counter; and a row hammer preventing logic to identify masking entries, on which a masking comparison is to be performed, among the entries on the basis of the safe bit counter, to determine a hit or miss on the basis of whether other bits except an MSB among address bits of an access-requested target row match other bits except an MSB among address bits of the masking entries, and to generate a control signal indicating an additional refresh on rows adjacent to rows corresponding to a masking entry whose hit count is greater than a threshold value.

Memory device including row hammer preventing circuitry and an operating method of the memory device

A semiconductor memory device includes a memory cell array including memory cell row, each of which includes volatile memory cells, a row hammer management circuit, a repair control circuit and a connection logic. The row hammer management circuit counts access addresses associated with the memory cell rows to store counting values, and determines a hammer address associated with least one of the memory cell rows, which is intensively accessed, based on the counting values. The repair control circuit includes repair controllers, each of which includes a defective address storage, and repairs a defective memory cell row among the memory cell rows. The connection logic connects first repair controllers, which are unused for storing defective addresses, among the plurality of repair controllers, to the row hammer management circuit. The row hammer management circuit uses the first repair controllers as a storage resource to store a portion of the access addresses.

Growing community of inventors

Hwaseong-si, South Korea

Jungmin You