Samsung Electronics Co., Ltd.

Jungjune Park

Chiweon Yoon

Youngmin Jo

Anil Kavala

Dongho Shin

Jeongdon Ihm

Byunghoon Jeong

Tongsung Kim

Jindo Byun

Junha Lee

Kyoungtae Kang

Joonyoung Kim

Hyunjin Kwon

Hyunsuk Kang

Hwanseok Ku

Cheolhui Lee

A data flip-flop circuit includes a flip-flop, a recovery latch and a cut-off transistor. The flip-flop stores a data signal that is input, using a clock signal and a virtual power supply voltage and provides the stored data signal as an output signal at an output node in response to a rising transition of the clock signal. The recovery latch is connected to a power supply voltage and a ground voltage, is connected to the flip-flop at the output node, stores the output signal internally in response to a first transition of a chip enable signal, recovers the stored output signal in response to end of a power gating interval based on the chip enable signal, and provides the recovered output signal to the flip-flop. The cut-off transistor floats the virtual power supply voltage provided to the flip-flop based on a first power gating signal.

Data flip-flop circuit of nonvolatile memory device and nonvolatile memory device including the same

A storage device includes a plurality of memory chips, a buffer chip connected to the plurality of memory chips, and a controller connected to the buffer chip. The buffer chip is configured to periodically receive a first command from the controller, and perform a DQS oscillator enable operation in response to the first command. At least one memory chip among the plurality of memory chips and the buffer chip are configured to perform write training or read training when the DQS oscillator enable operation is performed.

Nonvolatile memory package, storage device including the same, and method of operating thereof

A memory package includes a data input/output pin, a data strobe pin, a plurality of memory devices, and a buffer device. The data input/output pin receives a data signal. The data strobe pin receives a data strobe signal. The plurality of memory devices operate based on the data signal and the data strobe signal. The buffer device is between the data input/output pin, the data strobe pin and the plurality of memory devices, and performs a training operation based on training data and the data strobe signal in response to the data signal including the training data and the data strobe signal being received. During the training operation, the buffer device sets different delays on a plurality of sub-training data included in the training data, and the sub-training data on which the different delays are set are stored in different memory regions of the plurality of memory devices.

Memory package performing training operation using address-delay mapping and memory system including the same

Provided is a nonvolatile memory including a receive buffer configured to generate a buffer signal by comparing an input signal with a reference voltage, a reference voltage calibrator configured to generate a calibrated reference voltage code signal based on a reference voltage code signal and the buffer signal, and a reference voltage generator configured to generate a reference voltage corresponding to the calibrated reference voltage code signal. In addition, the read reference voltage calibrator includes a duty cycle monitor configured to generate a monitoring signal by measuring a duty cycle of the buffer signal, an up/down counter configured to generate a count number signal by comparing a reference duty cycle with a measurement duty cycle corresponding to the monitoring signal, and a code calculator configured to generate the calibrated reference voltage code signal based on the count number signal and the reference voltage code signal.

Nonvolatile memory device and memory system including the same

An apparatus and method for ZQ calibration, including determining a strong driver circuit and a weak driver circuit, which are related to an input/output (I/O) circuit connected to a signal pin, at power-up of the I/O circuit; providing a ZQ calibration code related to a sweep code to one from among the strong driver circuit and the weak driver circuit according to ZQ calibration conditions; and providing a ZQ calibration code related to a fixed code to an unselected circuit, thereby adjusting a termination resistance of the signal pin.

Apparatuses and methods for ZQ calibration

A high resolution impedance adjustment (ZQ) calibration method using a hidden least significant bit (HLSB) is provided. The high resolution ZQ calibration method generates a data input/output (DQ) code of n+1 bits without a calibration time increase by adding the hidden least significant bit (HLSB) to a ZQ code of n bits output in a ZQ calibration operation of an impedance adjustment (ZQ) pad. A change in a termination resistance of the DQ pad is reduced as small as possible by the DQ code of n+1 bits.

High resolution ZQ calibration method using hidden least significant bit (HLSB)

An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

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Seoul, South Korea

Jungjune Park