Samsung Electronics Co., Ltd.

Jungjoo Kim

Yongkwan Lee

Seunghwan Kim

Junwoo Park

Jongwan Kim

Hyunggil Baek

Taejun Jeon

Jongho Park

Junga Lee

Seung Hwan Kim

Junyoung Oh

Kyonghwan Koh

Sangsoo Kim

Hyunki Kim

Jun Young Oh

Dong-Ju Jang

Junhyeung Jo

Dongju Jang

A semiconductor package includes an interposer including an upper pad and an upper passivation layer partially covering the upper pad, a semiconductor chip disposed on the interposer, a conductor pattern disposed on the interposer, a guide pattern disposed on the interposer while including a main opening and at least one sub-opening connected to the main opening, a support disposed on the interposer while including a core portion and a peripheral portion surrounding the core portion, a lower surface of the support being disposed in the main opening of the guide pattern, an upper redistribution structure disposed on the semiconductor chip and connected to the conductor pattern and the guide pattern, and an encapsulant between the interposer and the upper redistribution structure. The encapsulant contacts an inner wall of the main opening, an inner wall of the at least one sub-opening and a side surface of the support.

Semiconductor packages having fixing members

A semiconductor package including a dielectric layer on a substrate and having an opening that partially exposes a top surface of the substrate, a capacitor chip on the substrate and in the opening of the dielectric layer, connection terminals between the substrate and the capacitor chip and connecting the substrate and the capacitor chip to each other, dielectric patches on the substrate and in the opening of the dielectric layer, and an under-fill filling a space between the substrate and the capacitor chip may be provided. The space between the substrate and the capacitor chip includes a first region, a second region, and a third region between the first and second regions. The connection terminals are on the first region and the second region. The dielectric patches are on the third region.

Semiconductor package

A semiconductor package is provided. The semiconductor package includes a package substrate, an interposer including a lower protective layer, conductive connectors connecting the package substrate to the interposer, a semiconductor chip arranged between the package substrate and the interposer, and cooling patches arranged between the semiconductor chip and the interposer and having cylindrical shapes, wherein each of the cooling patches includes the same material as each of the conductive connectors, a height of each of the cooling patches is less than or equal to a diameter of each of the cooling patches, and thermal conductivity of each of the cooling patches is greater than thermal conductivity of the lower protective layer.

A semiconductor package includes a package substrate including a base substrate including a redistribution layer, pads disposed on first and second surfaces of the base substrate and connected to the redistribution layer, and a protective layer having a mounting region in which first openings respectively exposing first pads among the pads and a second opening exposing second pads among the pads and a portion of the second surface are disposed on the second surface; a semiconductor chip disposed on the mounting region and connected to the pads through the first openings and the second opening; and a sealing material covering a portion of the semiconductor chip and extending into the second opening. Four first openings among the first openings are respectively disposed adjacent to respective corners of the mounting region. The second opening is disposed to divide the four first openings into at least two groups.

Package substrate and semiconductor package including the same

A semiconductor package includes; a package substrate, a semiconductor chip on the package substrate, an electromagnetic shield structure on the package substrate and including an upper cover covering an upper surface of the semiconductor chip and a side cover surrounding the semiconductor chip, and a sealing member contacting the semiconductor chip and the electromagnetic shield structure, wherein the side cover includes first through holes and the upper cover includes second through holes.

Semiconductor package including electromagnetic shield structure

A method of manufacturing a semiconductor package may include providing a substrate having first and second cutting regions respectively provided along first and second side portions opposite to each other and a mounting region between the first and second cutting regions is provided, disposing at least one semiconductor chip on the mounting region, forming a molding member on the substrate, and removing a dummy curl portion and at least portions of dummy runner portions from the molding member. The molding member may include a sealing portion, the dummy curl portion provided outside the second side portion of the substrate, and the plurality of dummy runner portions on the second cutting region to connect the sealing portion and the dummy curl portion. The substrate may include adhesion reducing pads in the second cutting region, which may contact the dummy runner portions respectively.

Molded product for semiconductor strip and method of manufacturing semiconductor package

A semiconductor package includes a lower substrate that includes a lower wiring layer; a semiconductor chip disposed on the lower substrate, and an upper substrate disposed on the semiconductor chip. The upper substrate includes a lower surface that faces the semiconductor chip, an upper wiring layer, and a plurality of protruding structures disposed below the lower surface. The lower surface of the upper substrate includes a cavity region that overlaps the semiconductor chip in a first direction, and a plurality of channel regions that extend from the cavity region to an edge of the upper substrate. The cavity region and the plurality of channel regions are defined by the plurality of protruding structures.

A semiconductor package includes a package substrate having a communication hole extending from an upper surface of the package substrate to a lower surface of the package substrate, a semiconductor chip attached to the upper surface of the package substrate, an auxiliary chip attached to the lower surface of the package substrate, external connection terminals attached to the lower surface of the package substrate and spaced apart from the auxiliary chip, and an encapsulant encapsulating the semiconductor chip and the auxiliary chip and filling the communication hole.

Semiconductor package having package substrate

A semiconductor package is provided. The semiconductor package includes: a first package substrate; a first semiconductor chip on the first package substrate; an interposer substrate including a lower surface facing the first package substrate, an upper surface opposite to the lower surface, and an upper conductive pad in the upper surface of the interposer substrate; a first dam structure on the upper surface of the interposer substrate and extending along an edge of the upper conductive pad; a first molding layer in contact with the lower and upper surfaces of the interposer substrate and with an outer wall of the first dam structure; and a conductive connector in contact with an inner wall of the at least one first dam structure and with the upper conductive pad.

Interposer and semiconductor package including the same

A semiconductor package includes a first substrate that includes a first trench on a recessed portion of a bottom surface of the first substrate and a first through hole extending through the first substrate to the first trench, a first semiconductor chip on the first substrate, a first capacitor chip in the first trench and on the first substrate, and a first molding layer on the first substrate and covering the first semiconductor chip. The first molding layer includes a first part that extends parallel to a top surface of the first substrate, a second part connected to the first part and extending vertically in the first through hole, and a third part connected to the second part and surrounding the first capacitor chip. A bottom surface of the third part is coplanar with the bottom surface of the first substrate.

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Daegu, South Korea

Jungjoo Kim