Samsung Electronics Co., Ltd.

Junghyun Hong

Youngjin Cho

Changkyu Seol

Hongrak Son

Pilsang Yoon

Younggeon Yoo

Chanho Yoon

Hyeokjun Choe

Jaehun Jang

Hanmin Cho

Suengchul Ryu

A storage device includes an accelerator including a first processor, and a storage controller that uses a buffer memory as a working memory and includes a second processor different in type from the first processor. The second processor is configured to establish a first communication path between the first processor and the buffer memory responsive to a request of the first processor, and the first processor is configured to access the buffer memory through the first communication path.

Storage devices including heterogeneous processors which share memory and methods of operating the same

A storage device includes a plurality of non-volatile memories; a volatile memory; a computing device configured to perform an operation on data provided by the plurality of non-volatile memories; and a storage controller including a resource manager configured to receive information about priority of tenants from a host, and to dynamically set resources of the plurality of non-volatile memories, the volatile memory, and the computing device based on the priority.

Storage device supporting multi-tenancy and operating method thereof

A neuromorphic package device includes a systolic array package and a controller. The systolic array package includes neuromorphic chips arranged in a systolic array along a first direction and a second direction. The controller communicates with a host controls the neuromorphic chips. Each of the neuromorphic chips sequentially transfers weights of a plurality layers of a neural network system in the first direction to store the weights. A first neuromorphic chip performs a calculation based on stored weights therein and an input data received in the second direction, and provides a result of the calculation to at least one of a second neuromorphic chip and a third neuromorphic chip which are adjacent to the first neuromorphic chip. The at least one of the second and third neuromorphic chips performs a calculation based on a provided result of the calculation and stored weights therein.

Neuromorphic package devices and neuromorphic computing systems

Growing community of inventors

Hwaseong-si, South Korea

Junghyun Hong