Duk San Neolux Co., Ltd.

Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Samsung Mobile Display Co., Ltd.

Duksan High Metal Co., Ltd.

Nhn Entertainment Corporation

Junghwan Park

Wonsam Kim

Soungyun Mun

Sunhee Lee

Bumsung Lee

Daesung Kim

Jungcheol Park

Hwasoon Jung

Dongha Kim

Jihun Byun

Yongwook Park

Hyeryeong Kim

Yuri Kim

Kwanhee Lee

Younghyun Kim

Mikyung Kim

Jaewan Jang

Yeonhee Choi

Kyungil Hong

Jungmin Lee

Eunkyung Kim

Daehyuk Choi

Jinuk Ju

Jeongkeun Park

Kiwon Kim

Sun-Hee Lee

Seokhyun Kim

Sechung Oh

Jangyeol Baek

Hyeon-Woo Jang

Se Chung Oh

Gyumin Lee

Sunpil Hwang

Heesun Ji

Keunnam Kim

Ho-in Ryu

Daeyup Shin

Heeju Shin

Seungwon Yeo

Jungwook Lee

Kyehee Yeom

Jong-Jin Ha

Seongje Park

Sungjin Kim

Soung Yun Mun

Kwan Hee Lee

Mi Kyung Kim

Yunsuk Lee

Sungjin Park

Jihye Kim

Yoosang Hwang

Jeehoon Han

Yun Suk Lee

Jaehoon Kim

Jung Wook Lee

Jeong-Heon Park

Kyungryun Kim

Sungchul Kim

Jung-Hoon Han

Junyong Noh

Joonmyoung Lee

Hyeongsun Hong

Yeon Hee Choi

Dongjin Kim

Hyoung Keun Park

Sugwoo Jung

Ki Woong Kim

Dongki Lee

Taeshick Kim

Jung Cheol Park

Mun Jae Lee

SeYoung Jang

Bongsoo Kim

Jae Wan Jang

Dae Hwan Oh

Kwangyoung Jung

Jonguk Kim

Byoungjae Bae

Sangyun Kim

Jangsun Yoo

Dae Kyu Shin

Dae Yup Shin

Yeonkyu Choi

Seul-gi Kim

Kiho So

Soonoh Park

Cheehwan Yang

Sanghun Chun

Jung Moo Lee

Jonggwang Park

Gyu Min Lee

Jinwoo Kim

Hyoengki Kim

Seung Soo Kim

Sungkwan Choi

Naoki Hase

Sanghwan Park

Jongheon Kim

Yong Seok Hong

Yonghee Lee

A magnetic memory device includes a first magnetic pattern and a second magnetic pattern that are sequentially stacked on a substrate, a tunnel barrier pattern between the first magnetic pattern and the second magnetic pattern, a lower electrode between the substrate and the first magnetic pattern, a blocking pattern between the lower electrode and the first magnetic pattern, a metal oxide pattern between the blocking pattern and the first magnetic pattern, and a buffer pattern between the metal oxide pattern and the first magnetic pattern. The lower electrode, the blocking pattern, the metal oxide pattern, and the buffer pattern include first, second, third, and fourth non-magnetic metals, respectively. The metal oxide pattern has an amorphous phase.

Magnetic memory devices

A method of fabricating a magnetic memory device comprises forming, on a substrate, a data storage structure including a bottom electrode, a magnetic tunnel junction pattern, and a top electrode, forming a first capping dielectric layer conformally covering lateral and top surfaces of the data storage structure, and forming a second capping dielectric layer on the first capping dielectric layer. The forming the first capping dielectric layer is performed by PECVD in which a first source gas, a first reaction gas, and a first purging gas are supplied. The forming the second capping dielectric layer Is performed by PECVD in which a second source gas, a second reaction gas, and a second purging gas are supplied. The first and second reaction gases are different from each other. The first and second purging gases are different from each other.

Magnetic memory device and method of fabricating the same

A magnetoresistive random access memory device includes a pinned layer; a tunnel barrier layer on the pinned layer; a free layer structure on the tunnel barrier layer, the free layer structure including a plurality of magnetic layers and a plurality of metal insertion layers between the magnetic layers; and an upper oxide layer on the free layer structure, wherein each of the metal insertion layers includes a non-magnetic metal material doped with a magnetic material, and the metal insertion layers are spaced apart from each other.

Magnetoresistive random access memory device having a metal layer doped with a magnetic material

A semiconductor device includes a substrate, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, channel structures penetrating the gate electrodes, extending in the first direction, and each including a channel layer, separation regions penetrating the gate electrodes, extending in the first direction and a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, and crack prevention layers disposed on at least a portion of the separation regions, wherein each of the separation regions includes a lower region and upper regions spaced apart from each other in the second direction on the lower region and protruding upwardly from the lower region, and wherein the crack prevention layers are in contact with upper surfaces of the upper regions.

Semiconductor devices comprising crack preventing layers and data storage systems including the same

A magnetic device includes a fixed layer including a fixed pattern, a free layer, and a tunnel barrier between the fixed layer and the free layer. The fixed pattern includes a first magnetic pattern, a second magnetic pattern, and a hybrid spacer, including a nonmagnetic material layer, between the first magnetic pattern and the second magnetic pattern, the nonmagnetic material including a plurality of magnetic nanoparticles dispersed therein.

Magnetic device

A magnetic memory device may include an interlayer insulating layer on a substrate, a bottom electrode contact disposed in the interlayer insulating layer, and a magnetic tunnel junction pattern on the bottom electrode contact. The bottom electrode contact may include a second region and a first region, which are sequentially disposed in a first direction perpendicular to a top surface of the substrate so that the second region is between the first region and the top surface of the substrate. A first width of the first region may be smaller than a second width of the second region, when measured in a second direction parallel to the top surface of the substrate.

Magnetic memory device

Data storage devices are provided. A data storage device includes a memory transistor on a substrate and a data storage structure electrically connected to the memory transistor. The data storage structure includes a magnetic tunnel junction pattern and a top electrode on the magnetic tunnel junction pattern. The top electrode includes a first top electrode and a second top electrode on the first top electrode, and the first and second top electrodes include the same metal nitride. The first top electrode includes first crystal grains of the metal nitride, and the second top electrode includes second crystal grains of the metal nitride. In a section of the top electrode, the number of the first crystal grains per a unit length is greater than the number of the second crystal grains per the unit length.

Data storage devices including a first top electrode and a different second top electrode thereon

A memory device includes: a first circuit; a second circuit; and an adaptive body bias generator configured to receive frequency detection information or temperature detection information, to apply a first forward body bias or a first reverse body bias to the first circuit in response to the frequency detection information or the temperature detection information, and to apply a second forward body bias or a second reverse body bias to the second circuit in response to the frequency detection information or the temperature detection information.

Memory device and an operating method thereof

A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

Semiconductor devices with peripheral gate structures

A semiconductor device includes a plurality of magnetic tunnel junction (MTJ) structures in an interlayer insulating layer on a substrate. A blocking layer is on the interlayer insulating layer and the plurality of MTJ structures. An upper insulating layer is on the blocking layer. An upper interconnection is on the upper insulating layer. An upper plug is connected to the upper interconnection and a corresponding one of the plurality of MTJ structures and extends into the upper insulating layer and the blocking layer. The blocking layer includes a material having a higher absorbance constant than the upper insulating layer.

Semiconductor device including blocking layer

The present invention provides the compound represented by Formula 1, an organic electric element comprising a first electrode, a second electrode, and an organic material layer formed between the first electrode and the second electrode, and electronic device thereof, and by comprising the compound represented by Formula 1 in the organic material layer, the driving voltage of the organic electronic device can be lowered, and the luminous efficiency and life time of the organic electronic device can be improved.

Compound for organic electric element, organic electric element comprising the same, and electronic device thereof

In a method of manufacturing a magnetoresistive random access memory, a memory structure may be formed on a substrate. The memory structure may include a lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode sequentially stacked. A protection layer including silicon nitride may be formed to cover a surface of the memory structure. The protection layer may be formed by a chemical vapor deposition process using plasma and introducing deposition gases including a silicon source gas, a nitrogen source gas containing no hydrogen and a dissociation gas. Damages of the MTJ structure may be decreased during forming the protection layer. Thus, the MRAM may have improved characteristics.

Method of manufacturing a magnetoresistive random access memory device

A method for wirelessly connecting devices performed in a wireless connection system implemented with a computer includes: providing a list of devices capable of remote access with a user account of a user; connecting devices based on the list of devices capable of remote access; automatically updating a list of folders in the connected devices and a list of files included in the folders; and integrally managing files included in the connected devices.

Method and system for wirelessly connecting devices

Provided is the compound represented by Formula 1, an organic electric element comprising a first electrode, a second electrode, and an organic material layer formed between the first electrode and the second electrode, and electronic device thereof, and by comprising the compound represented by Formula 1 in the organic material layer, the driving voltage of the organic electronic device can be lowered, and the luminous efficiency and life time of the organic electronic device can be improved.

Compound for organic electric element, organic electric element comprising the same and electronic device thereof

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Seoul, South Korea

Junghwan Park