Samsung Electronics Co., Ltd.

Junghwan Oh

Sangho Lee

Yoosang Hwang

Sunghee Han

Junwon Lee

Hyun Uk Park

Joon Hyuk Kim

Minhee Cho

Jinwoo Bae

Dongkyun Park

Han-young Kim

Jaehwan Cho

Wooil Kim

Sunwook Kim

Manhwee Jo

Disclosed is an integrated circuit, which counts parameters required for a dynamic voltage frequency scaling (DVFS) operation. The integrated circuit includes: an event block accessing a bus, which connects processing devices to each other, and outputting an event signal, based on data transmitted through the bus; a clock counter counting the number of clock signals received from a clock management unit; a plurality of performance counters respectively counting parameters used to calculate a workload, based on the event signal; an interface receiving an operation signal from the DVFS governor, which determines an operation frequency and an operation voltage of a processing device based on the workload, and transmitting the number of clock signals and the parameters to the DVFS governor; and a controller controlling operations of the event block, the clock counter, and the plurality of performance counters, based on the operation signal.

Integrated circuit, dynamic voltage and frequency scaling (DVFS) governor, and computing system including the same

A semiconductor device may include a bottom sub-electrode on a substrate, a top sub-electrode on the bottom sub-electrode, a dielectric layer covering the bottom and top sub-electrodes, and a plate electrode on the dielectric layer. The top sub-electrode may include a step extending from a side surface thereof, which is adjacent to the bottom sub-electrode, to an inner portion of the top sub-electrode. The top sub-electrode may include a lower portion at a level that is lower than the step and an upper portion at a level which is higher than the step. A maximum width of the lower portion may be narrower than a minimum width of the upper portion. The maximum width of the lower portion may be narrower than a width of a top end of the bottom sub-electrode. The bottom sub-electrode may include a recess in a region adjacent to the top sub-electrode.

Semiconductor device including storage node electrode including step and method of manufacturing the semiconductor device

A semiconductor device includes a plurality of capacitors disposed on a substrate and a support pattern supporting upper portions and lower portions of the capacitors. Each of the capacitors includes a lower electrode, an upper electrode, and a dielectric layer between the lower and upper electrodes. The lower electrode includes a first electrode portion electrically connected to the substrate and having a solid shape and a second electrode portion stacked on the first electrode portion and having a shape comprising an opening therein. The support pattern includes an upper pattern contacting sidewalls of top end portions of the lower electrodes and a lower pattern vertically spaced apart from the upper pattern. The lower pattern contacts sidewalls under the top end portions of the lower electrodes.

Semiconductor devices having hybrid capacitors and methods for fabricating the same

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Yongin-si, South Korea

Junghwan Oh