Samsung Display Co., Ltd.

Samsung Electronics Co., Ltd.

Junghwan Hwang

Hyuk Hwan Kim

Yang-Hwa Choi

Yanghwa Choi

Dae-Sik Lee

Yanguk Nam

Sehyoung Cho

Yoomi Kim

Chanwook Shim

Youngchul Jo

Jongjae Lee

Kwihyun Kim

Huigyeong Yun

Doo-young Lee

Hongmin Yoon

Jongdo Keum

Yoonsik Park

A display apparatus includes: a first substrate; a scan line extending in a first direction; a data line that extends in a second direction; a sensing line that extends in the second direction; a switching transistor electrically connected to the scan and the data lines; a driving transistor electrically connected to the switching transistor; a sensing transistor electrically connected to the driving transistor and electrically connected to the sensing line; a first insulating layer between the first substrate and a sensing semiconductor layer of the sensing transistor; a via insulating layer provided on the switching transistor, the driving transistor, and the sensing transistors; and a light-emitting diode including a first electrode, an emission layer, and a second electrode, the first electrode provided on the via insulating layer, wherein the sensing line is below the first insulating layer and overlaps the first electrode of the light-emitting diode.

Display apparatus

An embodiment of a display apparatus includes a scan driver, a pixel, a first scan line electrically connecting the scan driver to the pixel, a second scan line electrically connecting the scan driver to the pixel, and a third scan line electrically connecting the scan driver to the pixel, wherein in operation: the pixel receives first, second, and third scan signals from the scan driver by way of the first, second, and third scan lines, respectively; the first and second scan signals produce a display period of a frame period in the pixel; and the third scan signal produces a black insertion period of the frame period in the pixel.

Scan driver including plurality of first stages and plurality of second stages for outputting plurality of scan signals

A gate driver includes a plurality of active stages and a plurality of dummy stages. The active stage is configured to output a plurality of gate signals to a display region. The dummy stage is c connected to respective active stages and configured to output a plurality of dummy carry signals to the respective active stages. The active stage is configured to output the plurality of gate signals and a plurality of active carry signals. The plurality of dummy stages are configured to output the plurality of dummy carry signals, respectively, and not to output any gate signal.

Gate driving circuit and display apparatus including the same

An electronic device includes a pixel driving circuit to operate in a light emitting mode or a sensing mode and including a reference voltage line for receiving a reference voltage comprising a first reference voltage and a second reference voltage different from the first reference voltage and a light emitting diode including a first electrode, a light emitting element, and a second electrode. The light emitting diode has in an on-state or an off-state in the light emitting mode, the first reference voltage is applied to the reference voltage line in the light emitting mode, a first voltage is applied to the first electrode in the off-state, a second voltage is applied to the first electrode in the on-state, the sensing mode includes an initialization period and a sensing period, and the second reference voltage is applied to the reference voltage line in the initialization period.

Electronic device

A display device includes a plurality of pixels connected to a plurality of first scan lines, a plurality of second scan lines, and a plurality of data lines, where the pixels are arranged in a plurality of rows, a plurality of first stages connected to the first scan lines, a plurality of second stages connected to the second scan lines, and a data driver connected to the data lines. Each of the first scan lines is connected to pixels arranged in a corresponding row among the rows. Each of the second scan lines is commonly connected to pixels arranged in corresponding 8h rows among the plurality of rows, where h is a natural number.

Display device including pixels driven at different frequencies and driving method thereof

A display apparatus includes: a pixel part including a plurality of pixels, each of the plurality of pixels to receive a first scan signal and an emission signal; and a scan driver to output the first scan signal and the emission signal to each of the plurality of pixels. In a second driving mode in which the display apparatus is driven with a first driving frequency lower than a maximum driving frequency, the scan driver is to supply the first scan signal to the plurality of pixels according to the first driving frequency, and supply the emission signal to the plurality of pixels according to the maximum driving frequency.

A gate driver includes active stages that output gate signals to a display part and pre-stages connected to the active stages to output carry signals to the active stages. The pre-stages include a first pre-stage and a second pre-stage. The second pre-stage includes a Q node compensator that receives a clock signal from the first pre-stage and compensates for a voltage of a Q node based on the clock signal of the first pre-stage. The Q node compensator includes a feedback transistor that diode-connects a feedback input terminal, which receives the clock signal of the first pre-stage, to a feedback node of the second pre-stage. The feedback transistor includes a first electrode, a second electrode, and a third electrode, where the first electrode is connected to the feedback input terminal, the second electrode is connected to the first electrode, and the third electrode is connected to the feedback node.

Gate driver and display device including the same

Scan driver including plurality of first stages and plurality of second stages for outputting plurality of scan signals and display apparatus including the same

A pixel includes a first transistor, a second transistor, a third transistor, a capacitor, and a light emitting diode. During a non-emission period of a low frequency mode, the third transistor electrically connects a first terminal of the light emitting diode to an initialization voltage line in response to a second scan signal. An initialization voltage transferred from the initialization voltage line has a first voltage level during a normal mode different from the low frequency mode, and has a second voltage level different from the first voltage level during the non-emission period of the low frequency mode.

Display device

A display device includes a display panel including a pixel and a panel driver which drives the display panel at a first panel frequency in a first driving mode and drives the display panel at a second panel frequency in a second driving mode. The pixel includes a light emitting element and first, second, third, and fourth transistors. The first transistor is connected between a power line and the light emitting element. The second transistor is connected between a data line and the first transistor and receives a first scan signal. The third transistor is connected between the first transistor and an initialization voltage line and receives a second scan signal. The fourth transistor is connected between the first transistor and a reset voltage line and receives a third scan signal. The third scan signal is inactivated in the first driving mode and is activated in the second driving mode.

The present disclosure provides a display device. The display device includes a display panel including each of gate lines extending in a first direction, each of sub-gate lines which extends in a second direction crossing the first direction and is electrically connected to the gate line, each of first data lines, each of second data lines, each of first pixels, and each of second pixels, and a driving circuit for providing a gate signal and data signals, wherein a second capacitance between a second drain electrode and a second gate electrode of the second pixel is greater than a first capacitance between a first drain electrode and a first gate electrode of the first pixel.

Display device to improve display quality while minimizing bezel area

A display device includes: a display panel including data lines, gate lines, and pixels, the display panel is operated in an active period or in a blank period; and a driving circuit for driving the display panel, the driving circuit including: a signal controller for outputting clock control signals; a voltage generator for receiving the clock control signals, wherein the voltage generator outputs active clock signals synchronized with the clock control signals during the active period and outputs blank clock signals during the blank period; and an overcurrent detection circuit for receiving the clock control signals and the blank clock signals, the overcurrent detection circuit detects an overcurrent of the blank clock signals, and a phase difference between the clock control signals in the active period is different from a phase difference between the clock control signals in the blank period.

Display device and a method of driving a gate driver

A display device to display an image during frame intervals, and to display a blank image during a blank interval defined between the frame intervals, includes: a gate driving circuit including a plurality of stages, an ith stage (i is an integer greater than or equal to 2) from among the plurality of stages including a clock terminal to receive a clock signal, wherein the clock signal swings between a first clock voltage and a second clock voltage smaller than the first clock voltage during a normal interval corresponding to each of the frame intervals, and the clock signal is changed to a voltage lower than the second clock voltage during a stabilization interval corresponding to the blank interval.

Gate driving circuit having stabilization

A gate driving circuit comprising stages cascade-connected with each other and configured to output gate signals, a stage of the stages including a pull-up circuit configured to output a high voltage of a clock signal as a high voltage of a gate signal in response to a bootstrap voltage of a control node in a period of a frame period, a first discharging circuit configured to discharge a voltage of the control node to a first low voltage in response to a carry signal of at least one stage of the plurality of stages that is subsequent to the stage, and a second discharging circuit configured to discharge a voltage of the control node to a second low voltage being lower than the first low voltage in response to a carry signal of at least one stage of the plurality of stages that is subsequent to the stage.

Growing community of inventors

Cheonan-si, South Korea

Junghwan Hwang