Samsung Electronics Co., Ltd.

Nanyang Technological University

Seoul National University

Korea University Research and Business Foundation

Industry-University Cooperation Foundation Hanyang University

University of Seoul Industry Cooperation Foundation

St Pharm Co., Ltd.

Institut Pasteur Korea

Iucf-hyu (industry-university Cooperation Four

Junghwan Choi

Youngdon Choi

Younghoon Son

Jaewoo Park

Jindo Byun

Myoungbo Kwak

Hyunyoon Cho

Youngchul Cho

Seungjin Park

Hyungmin Jin

Junyoung Park

Eunseok Shin

Hojun Yoon

Won Young Lee

Joohwan Kim

Yongcheol Bae

Changkyu Seol

Joon-Young Park

Yoon-Joo Eom

Jueon Kim

Joosun Choi

Jihwan Hyun

Seongjin Jang

Sucheol Lee

Seunghoon Lee

Mingyu Lee

Changsik Yoo

Doobock Lee

Wonjoo Jung

Hyunsub Rie

Taehyoung Kim

Baek Jin Lim

Dongkyu Choi

Jinook Jung

Jungmin Park

Youngju Lee

Byungchul Kim

Pilsang Yoon

Jinsoo Lim

Hyejeong So

Jiyoup Kim

Daewook Kim

Hyun-Yoon Cho

Seungku Han

Youngdo Um

Kwangseob Shin

Changsoo Yoon

Sukhee Cho

Ji Hye Lee

Young Hee Choi

Dongjin Park

Chulwoo Kim

Taehwan Kim

Yohan Kim

Young Mi Kim

Jinwook Lee

Sungrae Kim

Minsu Jung

Sungrok Yoon

Young-Hoon Son

Taesung Lee

Soonyoung Lee

Eun Seok Shin

Chisung Oh

Chanki Kim

Byungkwon Kang

Yongsam Moon

Yoonsung Park

ChangSik Yoo

Garam Kim

Jeong-Kyoum Kim

Seokjae Lee

Jaesung An

Seokhun Hyun

Indal Song

Jinha Hwang

Woochul Jung

Baekjin Lim

Sungjin Son

Kwangsub Byun

Hyeokjun Choi

Junhan Choi

Young Kil Choi

Yongsun Lee

Ji Young Min

So Young Chang

Sun Hee Kang

Sun Ju Kong

Su Yeon Jo

Hyeonwoo Ahn

Jaegeol Lee

Soohwan Yoo

Jejoong Woo

Kyoungjun Roh

Sunjae Lim

Jungho Ko

Jaeha Kim

Jaewha Kim

Jongseon No

Ikjin Jo

A transmitter configured to receive first to N-th data in parallel and sequentially output the first to N-th data in response to first to N-th clock signals having different phases from each other, where N is an integer of at least 2, the transmitter including first to N-th data selectors including a first data selector and a second data selector in correspondence to the first to N-th data, each of the first to N-th data selectors being configured to perform a logical operation on one of the first to N-th data and the first to N-th clock signals and output a plurality of data selection signals, a first pre-driver in correspondence to at least two data selectors among the first to N-th data selectors, the first pre-driver being configured to receive the plurality of data selection signals from the at least two data selectors.

Transmitter, memory device and semiconductor device including the transmitter

An analog-to-digital conversion circuit includes an analog-to-digital converter (ADC) configured to receive an input signal and a first clock signal from an external source and to output a second clock signal and a digital output signal, a decision counter configured to increment a decision count value each time when the second clock signal received from the analog-to-digital converter is applied to the decision counter, a voltage control logic configured to output a control signal based on a result of comparing the decision count value with a reference count value, and a regulator configured to output an operation voltage, wherein the ADC is configured to adjust the cycle of the second clock signal, and the voltage control logic is configured to control the regulator to output a corrected operating voltage via the control signal.

Analog-to-digital conversion circuit and operating method of the same

Disclosed is a memory device which includes a pull-up driver that is connected between a power supply voltage and a first node, a T-coil circuit that is connected between the first node and a second node, an external resistor, and a ZQ controller that performs a ZQ calibration operation on the pull-up driver. The ZQ controller includes a path selecting circuit that selects one node among the first node and the second node, a comparing circuit that compares a voltage of the one node selected by the path selecting circuit with a pull-up reference voltage and outputs a comparison result, and a code generating circuit that generates a pull-up code for driving the pull-up driver, based on the comparison result. While the pull-up code is generated, the external resistor is connected between the second node and a ground voltage.

Memory device, electronic device, and operation method of memory device

An error correction code (ECC) decoder includes a syndrome generator and a burst error corrector. The syndrome generator generates global syndrome data and local syndrome data using input data and a parity check matrix based on a constacyclic code. The burst error corrector corrects a correctable error included in the input data using the global syndrome data and the local syndrome data. The input data includes a plurality of data bits arranged along a first direction and a second direction. The ECC decoder simultaneously corrects a single burst error and a multi-bit error. The single burst error occurs on two or more symbols arranged along the first direction in the input data, and each symbol includes two or more data bits. The multi-bit error randomly occurs on two or more data bits in the input data.

Error correction code decoder using constacyclic code, and memory device and memory system including the same

A receiver for receiving a data signal, comprising, an analog-to-digital converter configured to convert the data signal into digital data, a first-in-first-out buffer configured to determine a frame boundary of the digital data by referring to a comma index to output the digital data in units of data frames according to the determined frame boundary, a decision feedback equalizer configured to process a data frame output from the first-in-first-out buffer through a decision feedback equalization operation, wherein feedback data used in the decision feedback equalization operation of the data frame uses a predetermined fixed pattern, and a comma detector configured to generate the comma index by comparing a determined value of the data frame with the predetermined fixed pattern. The data frame may include a preceding data field in which a message is stored and a subsequent comma field having the same bit value as the fixed pattern.

Equalizers, communication systems and operating methods thereof

An electronic device may include a reception circuit configured to generate a plurality of reception data bits based on a voltage level of an analog signal received through a link, and to generate a plurality of bit reliability values indicating probabilities of error occurrence of the plurality of reception data bits based on the voltage level of the analog signal, an alignment circuit configured to group the plurality of reception data bits into a plurality of error correction code (ECC) symbols, and to generate a plurality of symbol reliability values indicating probabilities of error occurrence of the plurality of ECC symbols based on the plurality of bit reliability values, and a decoding circuit configured to correct errors of the plurality of ECC symbols based on the plurality of symbol reliability values.

Electronic devices and methods of operating the same

A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

Memory device and operating method of a memory device

In analog-to-digital conversion, a plurality of stages configured in a sequence to sequentially decide a plurality of bits in successive-approximation, each of the plurality of stages configured to operate in response to a corresponding clock among a plurality of clocks, and decide a corresponding bit among the plurality of bits from a corresponding positive pulse among a plurality of positive pulses and a corresponding negative pulse among a plurality of negative pulses; and a plurality of clock generating circuits respectively corresponding to a plurality of first stages among the plurality of stages, each of the plurality of clock generating circuit configured to generate the corresponding clock of a corresponding stage among the plurality of first stages based on an operation of a previous stage among the plurality of stages, the previous stage being before the corresponding stage in the sequence.

Time domain analog-to-digital converter and analog-to-digital converting method

A nonvolatile memory device may include a variable sampler configured to process a data signal in an amplifier mode or a sampler mode in response to a control signal, a selection circuit configured to transmit the data signal output from the variable sampler to a flip-flop via a delay unit or to the flip-flop via a path that bypasses the delay unit in response to the control signal, a converter configured to amplify a data strobe signal, a clock distribution network configured to transmit the data strobe signal amplified by the converter to the variable sampler or delay the amplified data strobe signal for a predetermined time and transmit the amplified data strobe signal to the flip-flop in response to the control signal, and a path controller configured to generate the control signal according to an input/output mode.

Nonvolatile memory device providing input/output compatibility and method for setting compatibility thereof

A receiver includes a voltage-to-time converter configured to sequentially output a first converted signal and a second converted signal based on a first signal, a second signal, and a time difference; a first time comparator configured to determine a first bit value based on a first first-arrival signal (FAS) and output first data including the first bit value; a delay time generator configured to select a non-target signal and a target signal based on the first bit value and from among the first converted signal and the second converted signal; and a second time comparator configured to determine a second bit value based on a second FAS and output second data including the second bit value.

Receiver, operation method thereof, and memory device

A semiconductor device includes a phase splitter configured to output a plurality of clock signals having different phases by using a plurality of external clock signals having different phases, a plurality of code generators configured to receive a pair of selection clock signals determined from the plurality of clock signals and to output a phase code corresponding to a phase difference error between the pair of selection clock signals, and a delay circuit configured to at least partly simultaneously adjust at least two of a rising edge and a falling edge of each of the plurality of external clock signals with reference to the phase code during a lock time.

Semiconductor device

An input/output circuit of a nonvolatile memory device and a nonvolatile memory device. The input/output circuit of a nonvolatile memory device includes a driver, which is configured to output data from the nonvolatile memory device to a data line, and a power gating circuit, which is connected between the driver and a power terminal or between the driver and a ground terminal and configured to block a leakage current of the driver. The power gating circuit includes a plurality of transistors electrically connected in parallel and having threshold voltages of different magnitudes, respectively.

Nonvolatile memory device including power gating circuit and input/output circuit of a nonvolatile memory device

There is provided a semiconductor device, which includes a calibration code generator circuit configured to generate a calibration code according to changes in external conditions, a first driver circuit configured to output a data signal with an impedance value controlled by the calibration code, an emphasis control circuit configured to generate an emphasis data signal using the data signal, and to change the calibration code according to an operating frequency to generate an emphasis code; and a second driver circuit configured to output the emphasis data signal with an impedance value controlled by the emphasis code.

Semiconductor device and method for preforming emphasis driving

A transmitter includes a data generator, a serializer, a transmission driver and a feedback circuit. The data generator generates a retimed data signal and retimed test data by adjusting a delay amount of each of an input data signal and a test data based on adjusted clock signals. The serializer generates a serial data signal by serializing the retimed data signal based on multi-phase clock signals. The transmission driver generates an output data signal based on the serial data signal and transmits the output data signal through a channel. The feedback circuit detects the setup margin and the hold margin of the retimed test data through a separate path different from a path of the retimed data signal and generates the adjusted clock signals by adjusting delay amounts of the multi-phase clock signals based on the detected setup margin and hold margin of the retimed test data.

Transmitter for ultra-high speed and storage device including the same

Disclosed is a method of operating an electronic device which communicates with an external electronic device. The method includes loading first user data including at least one first condition bit, first valid bits, and second valid bits, generating first and second intermediate data based on the first user data with reference to a target conversion rule of a conversion table of the electronic device, which corresponds to the at least one first condition bit, a sum of a first power value corresponding to the first intermediate data and a second power value corresponding to the second intermediate data being less than or equal to a power threshold value, generating first symbol data by performing first encoding on the first intermediate data, generating second symbol data by performing second encoding on the second intermediate data, and providing first encoded data including the first symbol data and the second symbol data.

Transmitting circuit providing encoded data, electronic device including the same, and method of operating the electronic device including the same

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Hwaseong-si, South Korea

Junghwan Choi