Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Junghwa Kim

Hyangsook Lee

Heeseok Lee

Eunha Lee

Jinseong Heo

Sanghyun Jo

Jooho Lee

Jeonggyu Song

Myoungho Jeong

Yongsung Kim

Haeryong Kim

Kyooho Jung

Taehwan Moon

Dongjin Yun

Jeongil Bang

Moonseob Jeong

Sung Jun Park

Shin Ae Jun

Jihoon Kim

Tae Gon Kim

Ji-Hyun Kim

Chan Kwak

Jaewon Jang

Hyukjae Kwon

Gajin Song

Seunggeol Nam

Kwanghee Kim

Nayoun Won

Taekhoon Kim

Wangwoo Lee

Mokwon Kim

Sewan Son

Dongho Jang

Minwoo Woo

Mi Jeong Kim

Mi Hye Lim

Dukhyun Choe

Youngnam Kwon

Dong Su Ko

Junso Pak

Kihyun Cho

Jun So Pak

Jiye Kim

Insun Jung

Hyeonsu Heo

Jisoo Hwang

Heejung Choi

Sunjung Byun

Daeun Yu

Byungseon An

Yonghui Lee

Young Mo Sung

A semiconductor package includes a first package having a first semiconductor chip, a second semiconductor chip and a core member including a through-hole. At least one of the first and second semiconductor chips is disposed in the through-hole. An encapsulant is disposed in the through-hole. A first redistribution layer is disposed above the core member and is electrically connected to the first and second semiconductor chips. A second redistribution layer is disposed under the core member and electrically connects the first and second semiconductor chips with an external PCB. Core vias penetrate the core member and electrically connect the first and second redistribution layers. A second package is disposed on the first package and includes a third semiconductor chip. A plurality of first electrical connection structures electrically connects the first and second packages. A plurality of second electrical connection structures electrically connects the semiconductor package with the external PCB.

Semiconductor package and method of manufacturing the same

A thin film structure includes a substrate; and a material layer having a fluorite structure, the material layer on the substrate and comprising crystals of which <112> crystal orientation is aligned in a normal direction of the substrate. The material layer may have ferroelectricity. The material layer may include the crystals of which the <112> crystal orientation is aligned in the normal direction of the substrate among all crystals of the material layer in a dominant ratio.

Thin film structure and semiconductor device comprising the same

A semiconductor package including a circuit board including a first wiring region, a die mounting region surrounding the first wiring region, and a second wiring region surrounding the die mounting region; a plurality of wiring balls on the first wiring region and the second wiring region and spaced apart from one another, the plurality of wiring balls including a plurality of first wiring balls on the first wiring region and a plurality of second wiring balls on the second wiring region; a die on the die mounting region, the die including a plurality of unit chips spaced apart from one another, and a die-through region corresponding to the first wiring region and exposing the first wiring balls; and a plurality of die balls on the die and the die mounting region, the plurality of die balls being spaced apart from one another and electrically coupled to the circuit board.

Semiconductor package for improving power integrity characteristics

A quantum dot including a semiconductor nanocrystal core including Group III-V compound, a first semiconductor nanocrystal shell disposed on the semiconductor nanocrystal core, the first semiconductor nanocrystal shell including zinc and selenium, and a second semiconductor nanocrystal shell disposed on the first semiconductor nanocrystal shell, the second semiconductor nanocrystal shell including zinc and sulfur, and a composite/electronic device. The quantum dot does not include cadmium and the first semiconductor nanocrystal shell includes a polyvalent metal dopant at an interface with the second semiconductor nanocrystal shell.

Quantum dots and electronic device including the same

Provided are dielectric thin-film structures and electronic devices including the same. The dielectric thin-film structure includes a substrate, and a dielectric layer provided on the substrate. The dielectric layer including a tetragonal crystal structure, and crystal grains including a proportion of the crystal grains preferentially oriented such that at least one of a <hk0>, <h00>, or <0k0> direction of a crystal lattice is parallel to or forms an angle of less than 45 degrees an out-of-plane orientation.

Dielectric thin-film structure and electronic device including the same

A semiconductor package includes: a first package including a first semiconductor chip; a second package under the first package, the second package including a second semiconductor chip; and a first interposer package between the first package and the second package, the first interposer package including: a power management integrated circuit (PMIC) configured to supply power to the first package and the second package; a core member having a through-hole in which the PMIC is disposed; a first redistribution layer on the core member, and electrically connected to the first package; a second redistribution layer under the core member, and electrically connected to the second package; core vias penetrating the core member, and electrically connecting the first redistribution layer with the second redistribution layer; and a first signal path electrically connecting the first package with the second package.

Provided are an electronic device including a dielectric layer having an adjusted crystal orientation and a method of manufacturing the electronic device. The electronic device includes a seed layer provided on a substrate and a dielectric layer provided on the seed layer. The seed layer includes crystal grains having aligned crystal orientations. The dielectric layer includes crystal grains having crystal orientations aligned in the same direction as the crystal orientations of the seed layer.

Electronic device and method of manufacturing the same

A semiconductor package may include a semiconductor chip including a chip pad, a redistribution structure including a redistribution insulation layer on the semiconductor chip and first redistribution patterns on a surface of the redistribution insulation layer, a passivation layer covering the first redistribution patterns, an UBM pattern on the passivation layer and extending into an opening of the passivation layer, a second redistribution pattern on the UBM pattern, conductive pillars on the second redistribution pattern, and a package connection terminal on the conductive pillars. The opening in the passivation layer may vertically overlap a portion of each of the first redistribution patterns. The second redistribution pattern may connect some of the first redistribution patterns to each other. Some of the conductive pillars may be connected to one another through the second redistribution pattern. The first redistribution patterns may be connected to the chip pad.

Semiconductor package and semiconductor device including the same

An electronic device includes a dielectric layer including crystal grains having aligned crystal orientations the dielectric layer may be between a substrate and a gate electrode. The dielectric layer may be between isolated first and second electrodes. A method of manufacturing an electronic device may include preparing a substrate having a channel layer, forming the dielectric layer on the channel layer, and forming a gate electrode on the dielectric layer.

Electronic devices and methods of manufacturing the same

A semiconductor device and a method of manufacturing the semiconductor device are included. The method of manufacturing the semiconductor device includes forming a hafnium oxide layer on a substrate and crystallizing the hafnium oxide layer by using a hafnium cobalt oxide layer as a seed layer. According to the method of manufacturing the semiconductor device, a thin-film hafnium oxide layer may be easily crystallized.

Semiconductor device and method of manufacturing the same

Provided are dielectric thin-film structures and electronic devices including the same. The dielectric thin-film structure includes a substrate, and a dielectric layer provided on the substrate. The dielectric layer including a tetragonal crystal structure, and crystal grains including a proportion of the crystal grains preferentially oriented such that at least one of a &#x3c;hk0&#x3e;, &#x3c;h00&#x3e;, or &#x3c;0k0&#x3e; direction of a crystal lattice is parallel to or forms an angle of less than 45 degrees an out-of-plane orientation.

A display panel includes: a substrate including an opening area, a display area surrounding the opening area, and an intermediate area between the opening area and the display area; a plurality of display elements in the display area and electrically connected to a thin film transistor; a plurality of wirings arranged along an edge of the opening area in the intermediate area; and at least one metal pattern spaced apart from the plurality of wirings in the intermediate area, the at least one metal pattern surrounding the opening area and having a ring shape opened at one side.

Display panel having opening area and method of manufacturing the same

An antenna module includes an antenna substrate, a fan-out package and first electrical connection structures. The antenna substrate includes a pattern layer including antenna and ground patterns, and a feeding layer under the pattern layer including a feeding network that supplies power to the antenna patterns. The fan-out package is under the antenna substrate and includes a semiconductor chip driving the antenna substrate, an encapsulant encapsulating some of the semiconductor chip, a first redistribution layer on the semiconductor chip electrically connecting the semiconductor chip with the antenna substrate, and a second redistribution layer under the semiconductor chip electrically connecting the semiconductor chip with external devices. The first electrical connection structures are between and electrically connect the antenna substrate and the fan-out package. A logic layer including logic patterns electrically connecting the pattern layer with the feeding layer in the antenna substrate in the first redistribution layer in the fan-out package.

Antenna module and electronic system including the same

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Yongin-si, South Korea

Junghwa Kim