Samsung Electronics Co., Ltd.

Junghoon Jun

Jeehoon Han

Kohji Kanamori

Younghwan Son

Seogoo Kang

Hyojoon Ryu

Jesuk Moon

Seungyoon Kim

Sanghun Chun

A semiconductor memory device including a substrate, first pad layers and a second pad layer on the substrate, a pattern structure including first openings on the first pad layers and a second opening on the second pad layer, and having first and second regions, gate electrodes on the pattern structure and each including a pad region, channel structures penetrating through the gate electrodes in the first region, gate contact plugs electrically connected to the gate electrodes through the pad region of each of the gate electrodes and extending in a vertical direction to penetrate the first openings and connected to the first pad layers, a source contact plug, extending in the vertical direction penetrating the second opening and connected to the second pad layer, and a source connection patter under the pattern structure and in contact with the source contact plug and the second pad layer may be provided.

Semiconductor devices and data storage systems including the same

A semiconductor device includes; gate layers stacked on a substrate, a channel layer extending through the gate layers, a string select gate layer disposed on the channel layer and a string select channel layer extending through the string select gate layer to contact the channel layer. The string select channel layer includes a first portion below the string select gate layer including a first protruding region, a second portion extending through the string select gate layer, and a third portion above the string select gate layer including a second protruding region.

Semiconductor devices with string select channel layer

Semiconductor devices with string select channel for improved upper connection

Growing community of inventors

Hwaseong-si, South Korea

Junghoon Jun