Samsung Electronics Co., Ltd.

Junghoon Bak

Woojin Kim

Junghwan Moon

Seowon Lee

Hyeongsun Hong

Boyoung Seo

Kwangil Shin

Myoungsu Son

Hong Hyun Kim

Nayoung Ji

A variable resistance memory device includes a first conductive line, a bipolar selection device on the first conductive line and electrically connected to the first conductive line, a second conductive line on the first conductive line and electrically connected to the bipolar selection device, a variable resistance layer on the second conductive line and electrically connected to the second conductive line, and a third conductive line on the variable resistance layer and electrically connected to the variable resistance layer.

Variable resistance memory device

Magnetic memory devices may include a substrate, a metal pattern extending in a first direction on the substrate, a magnetic tunnel junction pattern on the metal pattern, and an anti-oxidation layer between the metal pattern and the magnetic tunnel junction pattern. The magnetic tunnel junction pattern may include a first magnetic pattern, a tunnel barrier pattern, and a second magnetic pattern.

Magnetic memory devices for reducing electrical shorts between magnetic tunnel junction patterns

A magnetic memory device includes a device isolation layer on a substrate and defining an active region, a source region and a drain region apart from each other in the active region of the substrate, a channel portion in the active region of the substrate and between the source region and the drain region, a spin orbit torque (SOT)-inducing layer on the channel portion of the substrate, a magnetic tunnel junction (MTJ) structure on the SOT-inducing layer, the MTJ structure including a free layer on the SOT-inducing layer, a tunnel barrier layer on the free layer, and a pinned layer on the tunnel barrier, a word line on the MTJ structure, a source line electrically connected to the source region, and a bit line electrically connected to the drain region.

Magnetic memory device

A plurality of magnetic tunnel junction structures is arranged in rows and columns on a substrate. A plurality of top electrodes is disposed on the plurality of magnetic tunnel junction structures, respectively. A plurality of bit lines is disposed on the substrate. One of the plurality of bit lines is disposed between two magnetic tunnel junction structures, adjacent to each other, of the plurality of magnetic tunnel junction structures. A top surface of each of the plurality of bit lines is disposed at substantially the same level as a top surface of each of the plurality of top electrodes.

A lower dielectric layer is disposed on a semiconductor substrate. A plurality of peripheral lower wirings are disposed on a peripheral region of the semiconductor substrate and in the lower dielectric layer. An upper dielectric layer is disposed on the lower dielectric layer and covers the plurality of peripheral lower wirings. A mold layer is disposed on the upper dielectric layer and includes an etching stopper layer. A peripheral upper wiring penetrates the mold layer and the upper dielectric layer to be connected to at least one of the plurality of peripheral lower wirings. The peripheral upper wiring includes a wiring portion, a first via portion extending downwardly from a bottom surface of the wiring portion, and a second via portion extending downwardly from the bottom surface of the wiring portion.

Semiconductor memory device

A magnetic tunnel junction pattern includes a first magnetic layer, a tunnel barrier layer, a second magnetic layer, and a non-magnetic capping layer that are sequentially stacked on a substrate. A top electrode is disposed on the magnetic tunnel junction pattern. A bit line is disposed on the top electrode. The top electrode comprises a metal nitride pattern in contact with the non-magnetic capping layer and a metal pattern disposed on the metal nitride pattern.

Disclosed is a method of fabricating a magnetic memory device. The method of a fabricating a magnetic memory device includes forming an interlayer dielectric layer on a substrate, forming a sacrificial pattern in the interlayer dielectric layer, forming a magnetic tunnel junction pattern on the sacrificial pattern, after forming the magnetic tunnel junction pattern, selectively removing the sacrificial pattern to form a bottom contact region in the interlayer dielectric layer, and forming a bottom contact in the bottom contact region.

Growing community of inventors

Suwon-si, South Korea

Junghoon Bak