Samsung Electronics Co., Ltd.

Junggil Yang

Seungmin Song

Dong Il Bae

Geumjong Bae

Soojin Jeong

Sangsu Kim

Junbeom Park

Bongseok Suh

Sung Gi Hur

Minju Kim

Taeyong Kwon

Donghyi Koh

Inhyun Song

Jongho Lee

Dongkyu Lee

Myunggil Kang

Ohseong Kwon

Jooho Jung

Changjae Yang

An integrated circuit device including a substrate including first and second device regions; a first fin active region on the first device region; a second fin active region on the second device region; an isolation film covering side walls of the active regions; gate cut insulating patterns on the isolation film on the device regions; a gate line extending on the fin active regions, the gate line having a length limited by the gate cut insulating patterns; and an inter-region insulating pattern on the isolation film between the fin active regions and at least partially penetrating the gate line in a vertical direction, wherein the inter-region insulating pattern has a bottom surface proximate to the substrate, a top surface distal to the substrate, and a side wall linearly extending from the bottom to the top surface.

Integrated circuit device including N-channel metal-oxide semiconductor (NMOS) transistor region and a P-channel metal-oxide semiconductor (PMOS) transistor region

A semiconductor device includes: a substrate including an active region extending in a first direction; a gate electrode extending in a second direction and intersecting the active region, the gate electrode including first electrode layer(s) and a second electrode layer; channel layers spaced apart from each other in a third direction and at least partially surrounded by the gate electrode; source/drain regions, with at least one source/drain region on each side of the gate electrode and electrically connected to the channel layers; and air gap regions in the second electrode layer between the channel layers and between a lowermost channel layer and the active region in the third direction. The first electrode layer(s) or the second electrode layer has a first thickness between adjacent ones of the channel layers in the third direction, and has a second thickness greater than the first thickness on side surfaces of the channel layers.

Display device including a sensing layer for sensing an external input device and method of drving the same

A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.

Semiconductor devices

A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

Semiconductor device

A semiconductor device includes a first source/drain, a second source/drain isolated from direct contact with the first source/drain in a horizontal direction, a channel extending between the first source/drain and the second source/drain, a gate surrounding the channel, an upper inner spacer between the gate and the first source/drain and above the channel, and a lower inner spacer between the gate and the first source/drain and under the channel, in which the channel includes a base portion extending between the first source/drain and the second source/drain, an upper protrusion portion protruding upward from a top surface of the base portion, and a lower protrusion portion protruding downward from a bottom surface of the base portion, and a direction in which a top end of the upper protrusion portion is isolated from direct contact with a bottom end of the lower protrusion portion is oblique with respect to a vertical direction.

A semiconductor device includes a first source/drain structure having a first length in a horizontal direction, as viewed in a planar cross-sectional view, the horizontal direction being perpendicular to a vertical direction, a second source/drain structure having a second length in the horizontal direction, as viewed in the planar cross-sectional view, the second length being less than the first length, channels extending between the first source/drain structure and the second source/drain structure, the channels being spaced apart from each other in the vertical direction, at least one sacrificial pattern between adjacent ones of the channels, and a trench penetrating the channels and the at least one sacrificial pattern.

Method of manufacturing an integrated circuit device

Disclosed are semiconductor devices and their fabricating methods. The semiconductor device comprises first and second active patterns, a first channel pattern including first semiconductor patterns, a second channel pattern including second semiconductor patterns, a gate electrode on the first and second channel patterns, and a gate dielectric layer between the gate electrode and the first and second channel patterns. The gate electrode includes a first inner gate electrode between the first semiconductor patterns, a second inner gate electrode between the second semiconductor patterns, and an outer gate electrode outside the first and second semiconductor patterns. The first and second inner gate electrodes are on bottom surfaces of uppermost first and second semiconductor patterns. The outer gate electrode is on top surfaces and sidewalls of the uppermost first and second semiconductor patterns. The first and second inner gate electrodes have different work functions.

Semiconductor device including a field effect transistor and method of fabricating the same

Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.

Integrated circuit devices and methods of manufacturing the same

An integrated circuit includes a fin active region protruding from a substrate, a plurality of semiconductor patterns on an upper surface of the fin active region, a gate electrode that surrounds the plurality of semiconductor patterns and includes a main gate part on an uppermost one of the plurality of semiconductor patterns and sub gate parts between the plurality of semiconductor patterns, a spacer structure on a sidewall of the main gate part, and a source/drain region at a side of the gate electrode. The source/drain region is connected to the plurality of semiconductor patterns and contacts a bottom surface of the spacer structure. A top portion of the uppermost semiconductor pattern has a first width. A bottom portion of the uppermost semiconductor pattern has a second width smaller than the first width.

Integrated circuits and methods of manufacturing the same

Integrated circuit device

A semiconductor device including an active pattern on a substrate and extending lengthwise in a first direction parallel to an upper surface of the substrate; a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction; channels spaced apart from each other along a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure along the first direction; a source/drain layer on a portion of the active pattern adjacent to the gate structure in the first direction, the source/drain layer contacting the channels; inner spacers between the gate structure and the source/drain layer, the inner spacers contacting the source/drain layer; and channel connection portions between each of the inner spacers and the gate structure, the channel connection portions connecting the channels with each other.

Growing community of inventors

Suwon-si, South Korea

Junggil Yang