Samsung Electronics Co., Ltd.

Jung-Yong Choi

Jae-Hoon Kim

Jong-Hyun Choi

Kyu-Chan Lee

Sang-Jae Rhee

Young-Gu Kang

Ki-Ho Jang

Jong-Sik Na

A semiconductor memory device supporting a self refresh operation is disclosed and comprises an address buffer unit and an operation control unit. The address buffer unit may be enabled during the self refresh operation by a first external control signal to generate an internal address signal. The operation control unit controls the start of the self refresh operation in response to the internal address signal.

Semiconductor memory device having self refresh mode and related method of operation

An external high/low voltage compatible semiconductor memory device includes an internal voltage pad, an internal voltage generation circuit, and an internal voltage control signal generation circuit. The internal voltage pad connects a low external voltage with an internal voltage, and the internal voltage generation circuit generates an internal voltage in response to an internal voltage control signal and a high external voltage. The internal voltage control signal generation circuit generates an internal voltage control signal according to an high or low external voltage. Thus, a database of the semiconductor memory device can be managed without classifying the database into databases for the high voltage and databases for the low voltage because of the internal voltage control signal. In addition, the internal voltage level is stable because charges provided to the internal voltage are regulated according to a voltage level of the external voltage.

Semiconductor memory device having an internal voltage generation circuit for selectively generating an internal voltage according to an external voltage level

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Bundang-gu, South Korea

Jung-Yong Choi