Skhynix Inc.

Hynix Semiconductor Inc.

Jung Taek You

Sang Sic Yoon

Saeng Hwan Kim

Hong Joo Song

Chae Sung Lim

Kyu Dong Hwang

Byung Kuk Yoon

Min Joo Yoo

A memory device includes: a memory cell region including normal cells coupled to normal column selection lines, and row-hammer cells and redundancy cells respectively coupled to redundancy column selection lines; a repair control circuit configured to provide repair addresses and row-hammer flag signals, corresponding to repair information, according to a row address; and a column control circuit configured to activate at least one of the redundancy column selection lines according to the row-hammer flag signals or a comparison result of a column address and the repair addresses.

Memory device performing target refresh operation and operating method thereof

A semiconductor system according to an embodiment of the present disclosure includes a controller configured to output a command address, a first chip selection signal, and a second chip selection signal, and a semiconductor device, including a first rank and a second rank, configured to receive the command address, the first chip selection signal, and the second chip selection signal and configured to calibrate each termination resistance value based on the command address, the first chip selection signal, and the second chip selection signal. The first rank calibrates the termination resistance value of the first rank to a target resistance value based on the command address and the first chip selection signal when a write operation on the first rank is performed, and the first rank calibrates the termination resistance value of the first rank to a dynamic resistance value based on the second chip selection signal when a write operation on the second rank is performed.

Semiconductor devices and semiconductor systems calibrating termination resistance

A semiconductor system includes a controller configured to apply a command address, a first chip selection signal, and a second chip selection signal, and a semiconductor device including a first rank and a second rank configured to calibrate each termination resistance, based on the command address, the first chip selection signal, and the second chip selection signal.

Semiconductor device related to calibrating termination resistance

A semiconductor system includes a controller configured to transmit a command address and a plurality of read strobe signals, and a semiconductor device including a first rank and a second rank that are configured to receive the command address and the plurality of read strobe signals and to perform a write operation and a read operation based on the command address. In the semiconductor device, the first rank is configured to calibrate a termination resistance value of the first rank to a target resistance value when a write operation for the first rank is performed. In the semiconductor device, the first rank is configured to calibrate the termination resistance value of the first rank to a dynamic resistance value based on the plurality of read strobe signals when a write operation for the second rank is performed.

Semiconductor device related to calibrating a termination resistance

A semiconductor memory apparatus includes a plurality of cell arrays; and a use information storage block configured to determine whether a data write operation has already been performed for the plurality of cell arrays, and generate a plurality of control signals, wherein the semiconductor memory apparatus is configured to control a refresh operation for the plurality of cell arrays according to the plurality of control signals.

Semiconductor memory apparatus

A semiconductor circuit includes a test control unit configured to generate a driving activation signal and a sensing activation signal in response to a command and an address; a pad; a driver configured to drive the pad to a predetermined level in response to activation of the driving activation signal; and a sensing unit configured to compare a voltage level of the pad with a reference voltage in response to activation of the sensing activation signal, and output a sensing signal.

Semiconductor circuit and leakage current test system

A fuse circuit includes an E-fuse array including a plurality of E-fuse elements configured to store fuse data; a latch block including a plurality of latch groups configured to latch the fuse data read from the E-fuse array; and a control block configured to output latch reset signals corresponding to the plurality of latch groups in response to an apparatus reset signal and a clock signal, wherein the control block sequentially enables the latch reset signals.

Fuse circuit and semiconductor apparatus including the same

A repair system for a semiconductor apparatus includes a tester configured to generate memory repair data including a die identification information and repair addresses, and a command to perform a repair process; and a semiconductor apparatus including a plurality of dies configured to receive the memory repair data, wherein one of the dies corresponding to the die identification information performs a repair operation according to the repair addresses and the command.

Repair system for semiconductor apparatus and repair method using the same

A data write circuit of a semiconductor apparatus includes a plurality of latches configured to latch a plurality of data in response to activation of a plurality of control signals and output the latched data to data lines; and a control unit configured to generate the plurality of control signals to be activated at different timings, such that partial data input at relatively earlier timing among the plurality of data is latched at earlier timing than the other data by a portion of the plurality of latches.

Semiconductor apparatus and data write circuit of semiconductor apparatus for preventing transmission error

A repair control circuit and a semiconductor integrated circuit using the same, which can reduce test time, are provided. The semiconductor integrated circuit includes a plurality of memory blocks in which a plurality of word lines are arranged, a plurality of word line drivers driving one or more of the plurality of word lines in response to a plurality of memory block selection signals, and a repair control circuit determining whether to perform a repair through comparison of repair addresses generated in response to surplus addresses and the plurality of memory block selection signals with external addresses.

Repair control circuit and semiconductor integrated circuit using the same

An anti-fuse control circuit includes a first power supply voltage application unit, a second power supply voltage application unit and a control unit. The first power supply voltage application unit configured to selectively apply first power supply voltage to an output node in response to a power up signal. The second power supply voltage application unit configured to selectively apply second power supply voltage to the output node in response to a program signal. The control unit configured to control a connection between the output node and an anti-fuse in response to the power up signal when the program signal is inactivated.

Growing community of inventors

Icheon-si, South Korea

Jung Taek You