Samsung Electronics Co., Ltd.

Jung-Taek Lim

Young-Jee Yoon

Sung-Hong Park

Chung-Sam Jun

Jin-Soo Kim

Tae-Sung Kim

Dong-Chun Lee

Sung-Joon Byun

Soo-Won Lee

In an embodiment of a method of inspecting a substrate, the substrate on which minute structures are formed is divided into a plurality of inspection regions. A main inspection region among the inspection regions is selected. A main image of the main inspection region and sub-images of sub-inspection regions adjacent to the main inspection region are obtained. An average image of the main image and the sub-images is obtained. The average image is then compared with the main image to detect defects in the main inspection region. Gray levels may be used. The average image may have improved quality so that the defects in the selected inspection region may be rapidly and accurately detected. This process has an improved reliability. Further, the number of inspecting processes for the substrate may be reduced. And a line for the inspection process may be automated so that a worker-free line may be established.

Method and apparatus for inspecting a substrate

In an embodiment, a method of scanning a substrate, and a method and an apparatus for analyzing crystal characteristics are disclosed. A sequential scan on the scan areas using a first electron beam and a second electron beam are repeatedly performed. The electrons accumulated in the scan areas by the first electron beam are removed from the scan areas by the second electron beam. When a size of the scan area is substantially the same as a spot size of the first electron beam, adjacent scan areas partially overlap each other. When each of the scan areas is larger than a spot size of the first electron beam, the adjacent scan areas do not overlap each other. Images of the scan areas are generated using back-scattered electrons emitted from each of the scan areas by irradiating the first electron beam to analyze crystal characteristics of circuit patterns on the substrate.

Method of scanning a substrate, and method and apparatus for analyzing crystal characteristics

In the methods of compensating for an alignment error during fabrication of structures on semiconductor substrates, a conductive pattern structure is formed at a first position on a first semiconductor substrate. The conductive pattern structure includes a grid of first and second conductive patterns arranged as columns and intersecting rows with openings bounded therebetween. A first conductive contact structure overlaps the conductive pattern structure, and includes a plurality of spaced apart conductive contacts arranged as a grid of rows and columns that can be tilted at a non-zero angle relative to the grid of the conductive pattern structure. A determination is made as to whether the first conductive contact structure is electrically connected to the conductive pattern structure. A second conductive contact structure is formed at a position on a second semiconductor substrate that is determined in response to the determination of whether the first conductive contact structure is electrically connected to the conductive pattern structure.

Methods of compensating for an alignment error during fabrication of structures on semiconductor substrates

An etching system and method. In the method, layers are etched on a plurality of substrates using a single amount of etchant to form a predetermined pattern on each of the layers, wherein an etching period varies according to an accumulated process number of substrates. The system includes an etching equipment including an etching processor for etching layers on a plurality of substrates using a single amount of etchant to form a predetermined pattern on each of the layers, and a loader for temporarily holding cassettes in which the substrates are stored; and a controller for controlling operations of the etching equipment. The etching equipment changes an etching period according to an accumulated process number of the substrates.

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Gyeonggi-do, South Korea

Jung-Taek Lim