Samsung Display Co., Ltd.

Samsung Electronics Co., Ltd.

Markany Inc.

Dongwoo Fine-chem

Jung-Soo Lee

Ji-Hyun Kim

Jeong-Min Park

Jun Su Chun

Jeong Min Park

Sung Kyun Park

Jeongmin Park

Sung-Kyun Park

Ki-Hyun Cho

Sang Gab Kim

Jin-Ho Ju

Jin Ho Ju

Jinho Ju

Je Hyeong Park

Jong-Uk Choi

Dong-Won Woo

Dong-Min Kim

Sanggab Kim

Sungkyun Park

Jung Hwan Bang

Byung-Uk Kim

Gwui-Hyun Park

Dong-Sub Kim

You Young Jin

Ho-Yeon Lee

Hyoc-Min Youn

Junhong Park

In-Ho Yu

Han-Ho Lee

Seong-Hyeon Kim

Sil-Kuy Lim

Eun-Sang Lee

Eun Jeagal

Jin-Sun Kim

Seung-Ki Kim

Tai-Hoon Yeo

Kyoung-Heon Lee

Gwang-Pil Lee

Won-Young Chang

Jun-Hong Park

A display apparatus includes a base substrate, a first conductive pattern disposed on the base substrate, a first insulation layer disposed on the base substrate to cover the first conductive pattern, where a first contact hole is defined through the first insulation layer, a first pattern disposed on the first insulation layer, where the first pattern is in contact with the first conductive pattern through the first contact hole, a first filling pattern disposed in a recess of the first pattern which is defined by the first contact hole, a second insulation layer disposed on the first pattern and the first insulation layer, where a second contact hole overlapping the first contact hole is defined through the second insulation layer, and a second conductive pattern electrically connected to the first pattern through the second contact hole.

Display apparatus and method of manufacturing the same

A display apparatus includes a substrate and a plurality of pixels disposed on the substrate. Each pixel includes a gate electrode on the substrate, a common electrode insulated from the gate electrode on the substrate, a first insulating layer covering the gate electrode and the common electrode, a semiconductor pattern disposed on the first insulating layer to overlap with the gate electrode, source and drain electrodes disposed on the semiconductor pattern and spaced apart from each other, and a pixel electrode disposed on the first insulating layer to cover the drain electrode and form an electric field with the common electrode. The display apparatus may be manufactured by first to fourth photolithography processes using first to fourth masks, and the first mask may be a slit mask or a diffraction mask.

Display substrates, methods of manufacturing the same and display devices including the same disclosed. In one aspect, a display substrate includes a base substrate and a stack structure over the base substrate, the stack structure including an active pattern, a gate electrode and a plurality of insulation layers. The display substrate also includes a plurality of wirings over the stack structure and a plurality of colored capping patterns over respective ones of the wirings.

Display substrates, methods of manufacturing the same and display devices including the same

A thin film transistor substrate includes a gate electrode on a base substrate, an active pattern on the gate electrode, a source electrode on a first end of the active pattern, a drain electrode on a second end of the active pattern, an organic insulation layer on the source electrode and the drain electrode, and a transparent electrode contacting the drain electrode through a contact opening in the organic insulation layer. The drain electrode is spaced from the source electrode. The organic insulation layer includes a first thickness portion around the contact opening and a second thickness portion adjacent to the first thickness portion. The second thickness portion has a thickness greater than that of the first thickness portion.

Thin film transistor substrate, liquid crystal display device having the same and method of manufacturing the same

A thin film transistor array panel includes a substrate, a gate line and a gate pad disposed on the substrate, a gate insulating layer disposed on the gate line and the gate pad, a data line and a data pad disposed on the gate insulating layer, an organic layer disposed on the data line and the data pad, and a connecting member disposed on one of the gate pad and the data pad, in which the organic layer includes a first portion overlapping the connecting member and a second portion not overlapping the connecting member, and a height of the first portion of the organic layer is greater than a height of the second portion of the organic layer.

Thin film transistor array panel and manufacturing method thereof

A display panel includes: a substrate including red, green, blue and white sub-pixel areas; red, green and blue color filter layers respectively in the red, green and blue sub-pixel areas; and a dummy color filter layer in the white sub-pixel area. The dummy color filter layer is adjacent to at least one of the red color filter layer, the green color filter layer, and the blue color filter layer, and the dummy color filter layer forms a step with the adjacent color filter layer.

Display panel and liquid crystal display including the same

A display device and method of fabricating the same are disclosed. In one aspect, the display device includes a substrate, a black matrix formed over the substrate, and a transparent electrode formed over the substrate. The black matrix and the transparent electrode have first and second areas, respectively. The sum of the first and second areas is substantially equal to the surface area of the substrate.

Display device and method of fabricating the same

The present disclosure provides a thin film transistor array. In an exemplary embodiment, the thin film transistor array includes: a substrate; a gate line including a gate pad and disposed on the substrate; a gate insulating layer disposed on the gate line and the gate pad; a data line including a data pad and disposed on the gate insulating layer; a first passivation layer disposed on the data line; a first electrode disposed on the first passivation layer; a second passivation layer disposed on the first electrode; and a second electrode disposed on the second passivation layer. The gate pad is exposed through a first contact hole, and the gate insulating layer, the first passivation layer, and the second passivation layer include at least a portion of the first contact hole.

Thin film transistor array panel

A photoresist composition includes about 0.1 to about 30 parts by weight of a photo-initiator, about 1 to 50 parts by weight of a first acrylate monomer including at least five functional groups, about 1 to 50 parts by weight of a second acrylate monomer including at most four functional groups with respect to about 100 parts by weight of an acryl-copolymer.

Photoresist composition and method of manufacturing a thin film transistor substrate

A method of manufacturing a pattern includes forming a pattern material layer on a substrate, forming a protective layer on the pattern material layer, forming a resist layer on the protective layer, selectively exposing the resist layer to light, and developing the selectively exposed resist layer.

Method for manufacturing pattern using chemically amplified resist

A photoresist composition, a method of forming a pattern, and a method of manufacturing a thin film transistor substrate, the composition including a solvent, a novolak resin, a diazide-based photo-sensitizer, an acryl compound represented by the following Chemical Formula 1: 

Photoresist composition, method of forming a pattern and method of manufacturing a thin film transistor substrate

A thin film transistor (TFT) array panel and a manufacturing method thereof are disclosed. A contact hole may be formed to expose a pad disposed on a substrate of the TFT array panel. A first layer of a connecting member is formed with the same layer as a first field generating electrode and is disposed in the contact hole. A second passivation layer is disposed in the TFT array panel, but is removed at a region where the contact hole is formed and portions of the second passivation layer that cover the first layer of the connecting member. A second layer of the connecting member is formed on the first layer of the connecting member.

A display apparatus includes a first substrate, a second substrate disposed on the first substrate, and a controllable layer disposed between the first and second substrates. The first substrate includes a pixel. The pixel includes a display region and a non-display region. The first substrate further includes: a transistor disposed in the non-display region; a protection layer disposed on and covering the transistor; a first electrode disposed on the protection layer; and a second electrode disposed on the first electrode, the second electrode being insulated from the first electrode and including a slit disposed in the display region. One of the first electrode and the second electrode is electrically connected to the transistor via a contact hole extending through the protection layer. The other of the first electrode and the second electrode is configured to receive a common voltage. The contact hole and the slit do not overlap one another.

Display panel and display apparatus including the same

A thin film transistor array panel according to an exemplary embodiment of the present invention includes: an insulation substrate; a thin film transistor disposed on the insulation substrate, wherein the thin film transistor includes a first electrode; a first contact hole pattern having a first width, wherein the first contact hole pattern exposes a portion of the first electrode, and a first contact hole to expose the portion of the first electrode, wherein an inner sidewall of the first contact hole pattern constitutes a first portion of the first contact hole.

Thin film transistor panel and method for manufacturing the same

Instead of forming contact holes the same way in both the non-image forming peripheral area (PA) and the image forming display area of a thin film transistor array panel, contact holes in the DA are formed to be substantially smaller than those in the PA for thereby improving an aperture ratio of the corresponding display device. In an exemplary embodiment, an inorganic gate insulating layer is not etched in the DA and only an inorganic first passivation layer among inorganic insulating layers positioned in the DA is etched to allow communication between the drain electrode and the corresponding field generating electrode. On the other hand, in the peripheral area, plural inorganic insulating layers such as the gate insulating layer, the first passivation layer, and the second passivation layer positioned on the gate wire and the data wire are simultaneously etched to form second contact holes and third contact holes exposing respective gate pads and data pads.

Growing community of inventors

Seoul, South Korea

Jung-Soo Lee