Samsung Electronics Co., Ltd.

Chonnam National University

Jung-Sik Kim

Ho-Cheol Lee

Jung-Bae Lee

Cheol Su Kim

Sang-Ho Shin

Moon-Ki Huh

Hyun-Chul Woo

Dong-Hyuk Lee

Jang-Woo Ryu

Chi-Sung Oh

Seong-Taek Hwang

Chang-Ho Lee

Jong-Hyun Park

Young-Min Lee

Soo-Hyung Kim

Dong-Il Seo

Joo-sun Choi

Hyung-Dong Kim

Hee-bum Ahn

Jong-Wook Park

Tae-seong Jang

Sung-Min Yim

Chan-yong Lee

Kwun-soo Cheon

Guee-Sang Lee

Han-Gu Sohn

Mi-Jo Kim

Soo-Man Hwang

Yun-Hee Shin

Hyung-Jung Yang

Joung-wook Moon

Young-min Jang

Min-Ki Na

Myung-Hun Lee

Jun-Sik Lim

Jong-Mun Jeong

An apparatus and method for controlling a screen display in a portable terminal are provided. The apparatus includes a display unit, an input unit, a memory unit, a magnification identifying unit, and a controller. The display unit displays a screen display having a controlled magnification level. The input unit sets a zoom-in or zoom-out point on the screen display. The memory unit stores reference information for determining a zoom-in or zoom-out magnification level of the screen display. The magnification identifying unit measures a tilt of the portable terminal, and determines control or non-control of a magnification level of the screen display using the measured tilt. The controller controls the screen display according to the identified magnification level.

Apparatus and method for controlling a screen display in portable terminal

A semiconductor memory device includes a cell array and a refresh controller coupled to the cell array. The refresh controller is configured to insert at least one insertion refresh address in a first refresh address sequence based on address information about the cell array to generate a second refresh address sequence and to apply the second refresh address sequence to the cell array, such that selected cells may be refreshed more frequently without increasing an overall refresh rate.

Semiconductor memory device that controls refresh period, memory system and operating method thereof

A memory device to correct a defect cell generated after packing is performed includes a memory cell array in which a plurality of memory cells are arranged, a repair circuit unit including a first storage unit to store defect cell information in the memory cell array, and a fuse circuit unit including a second storage unit that is programmed according to the defect cell information stored in the first storage unit. The first storage unit includes a volatile memory device, and the second storage unit includes a non-volatile memory device.

Memory device to correct defect cell generated after packaging

A semiconductor memory device which stores refresh period information thereby adjusting a refresh period and a method of operating the same. The semiconductor memory device includes a cell array and a refresh information storing unit. The cell array includes one or more cell regions each having a plurality of memory cells. The refresh information storing unit is configured to store first information including a first refresh period and second information including a second refresh period in correspondence to each of the cell regions. Memory cells included in each of the cell regions are refreshed at the first refresh period according to the first information in a first refresh time band and are refreshed at the second refresh period according to the second information in a second refresh time band.

Semiconductor memory device storing refresh period information and operating method thereof

A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.

Semiconductor memory device having improved refresh characteristics

A semiconductor device, memory device, system, and method of using a stacked structure for stably transmitting signals among a plurality of semiconductor layers is disclosed. The device includes at least a first semiconductor chip including a first temperature sensor circuit configured to output first temperature information related to the first semiconductor chip, and at least one through substrate via.

Semiconductor device with stacked structure having through electrode, semiconductor memory device, semiconductor memory system, and operating method thereof

Semiconductor devices configured to test connectivity of micro bumps including one or more micro bumps and a boundary scan test block for testing connectivity of the micro bumps by scanning data input to the micro bumps and outputting the scanned data. The semiconductor device may include a first chip including solder balls and at least one or more switches electrically coupled with the respective solder balls, and a second chip stacked on top of the first chip and electrically coupled with the switches in direct access mode, including micro bumps that input/output signals transmitted from/to the solder balls.

Semiconductor devices and semiconductor packages

Disclosed is a method for retrieving a label in a portable terminal. The method includes obtaining a label image photographed through a camera, extracting characters included in the label image and recognizing the extracted characters, detecting at least one label including the recognized character from a label database including multiple labels and information on the multiple labels and constituting a preliminary label candidate group including said at least one label, detecting an image characteristic of the label image, detecting at least one label having an image characteristic, which is similar with the detected image characteristic, from the preliminary label candidate group, and constituting a final label candidate group, and providing each of said at least one label included in the final label candidate group and detailed information corresponding to each of said at least one label.

Method and apparatus for retrieving label

An internal power generating system for a semiconductor device is disclosed. The device may include a plurality of channels. The system comprises a reference voltage generator configured to generate a reference voltage. The system further comprises a plurality of internal power generators that are allocated to the plurality of channels in one-to-one correspondence and that are configured to commonly use the reference voltage generated by the reference voltage generator. Each internal power generator may be configured to receive a fed back internal power voltage, to compare the fed back internal power voltage to the reference voltage, and to generate an internal power voltage based on the comparison. The system further comprises a plurality of channel state detectors that are allocated to the plurality of channels in one-to-one correspondence, and that are configured to respectively detect operation states of the plurality of channels based on separate respective sets of command signals for each channel. The system additional comprises a plurality of internal power controllers that are allocated to the plurality of channels in one-to-one correspondence, and that are configured to respectively control driving capabilities for the internal power voltages according to the detected operation states.

Internal power generating apparatus, multichannel memory including the same, and processing system employing the multichannel memory

Disclosed are a semiconductor device capable of testing memory cells and a test method. The semiconductor device includes a plurality of terminals, each terminal being configured to receive similar data during a test mode, a plurality of buffers, each buffer being configured to receive data from a corresponding terminal and output either the data or changed data to a corresponding memory cells in response to a control signal, and a control unit configured to generate a plurality of control signals, each control signal being respectively applied to a corresponding buffer.

Semiconductor device testing memory cells and test method

A multi-port memory device includes first and second ports, a first dedicated memory area assigned to the first port, a plurality of shared memory units having shared access by the first and second ports, a first set of I/O lines for the first dedicated memory area, and a second set of I/O lines for the shared memory units with the second set having more I/O lines than the first set. For example, the second set has N times more I/O lines than the first set, with N being a number of ports of the multi-port memory device or with N being a number of shared memory banks in a shared memory area.

Routing access with minimized bus area in multi-port memory device

A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.

Multipath accessible semiconductor memory device with host interface between processors

Provided are a charge transfer switch circuit for selectively controlling body bias voltage of a charge transfer device, and a boosted voltage generating circuit having the same. The charge transfer switch circuit may include a capacitor whose voltage is boosted based on first and second control signals, a first transistor connected between a supply voltage and the capacitor and having a gate receiving a precharge signal, a second transistor connected between a first node and a second node and having a gate connected to a terminal of the capacitor, a third transistor connected between the first node and a bulk voltage of the second transistor and having a gate receiving the first control signal, and a fourth transistor connected between the bulk voltage of the second transistor and a ground voltage and having a gate receiving the second control signal.

Growing community of inventors

Seoul, South Korea

Jung-Sik Kim