Samsung Electronics Co., Ltd.

Jung-Shik Heo

Dong-Suk Shin

Ho-Young Reho Lee

Myung-Sun Kim

Yong-Kuk Jeong

Hoi-Sung Chung

Dong-Hyuk Kim

Jung-Sung Hwang

Il-young Yoon

Seok-Youn Kim

Do-Hyun Kwun

A method of manufacturing a semiconductor device includes forming a gate electrode on a semiconductor substrate and a sidewall spacer on the gate electrode. Then, a portion of the semiconductor substrate at both sides of the sidewall spacer is partially etched to form a trench. A SiGe mixed crystal layer is formed in the trench. A silicon layer is formed on the SiGe mixed crystal layer. A portion of the silicon layer is partially etched using an etching solution having different etching rates in accordance with a crystal direction of a face of the silicon layer to form a capping layer including a silicon facet having an (111) inclined face.

Methods of manufacturing semiconductor devices including forming (111) facets in silicon capping layers on source/drain regions

A vibration control pedestal and an installation method thereof are disclosed, including a method for reducing particles and vibrations while moving equipment, including semiconductor equipment, from one vibration control pedestal to another. The vibration control pedestal includes an equipment support body having at least two equipment support cells. A cell connection unit passes through side surfaces of the equipment support cells and connects the equipment support cells to each other. A bottom structure installed under the equipment support body braces the equipment support body.

Vibration control pedestal and installation method thereof

A semiconductor device includes a sidewall oxide layer covering an inner wall of a trench, a nitride liner on the sidewall oxide layer and a gap-fill insulating layer filling the trench on the nitride liner. A first impurity doped oxide layer is provided at edge regions of both end portions of the sidewall oxide layer so as to extend from an entry of the trench adjacent to an upper surface of the substrate to the nitride liner. A dent filling insulating layer is provided on the nitride liner in the trench to protect a surface of the first impurity doped oxide layer. Related methods are also disclosed.

Shallow trench isolation structures for semiconductor devices including wet etch barriers

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Seoul, South Korea

Jung-Shik Heo