Intel Corporation

Jung S Kang

James E Breisch

Berni W Landau

Yuan-Liang Li

Dong Zhong

Kevin M Connolly

Akira Kakizawa

Jiangqi He

Cory E Weber

Shaofeng Yu

Mark A Beiley

Zong-Fu Li

Jianggi He

Joseph W Parks, Jr

Kaladhar Radhakrishnan

Edward John Bawolek

Robert C Sundahl

Hyunjun Kim

Joel A Auernheimer

Yi-Feng Liu

Michael M DeSmith

John Tang

Stephen Bradford Gospe

Jack S Uppal

Prashant D Parmar

Peter Peide Jeng

Md Monzur Hossain

Shamala A Chikamenahalli

In an integrated circuit design, flex tape is used to provide signal ingress/egress to/from the integrated circuit design. Various architectures for the signal ingress/egress via flex tape is provided. In one embodiment, coaxial design is provided. In another embodiment, a coplanar waveguide design is provided.

Flex tape architecture for integrated circuit signal ingress/egress

A plurality of N-doped strip portions are formed alternating with a plurality of P-doped regions. When a voltage is applied to the N-doped strip portions, a capacitance is created between the N-doped strip portions and the P-doped strip portions. A capacitance is also created between the N-doped strip portions and the underlying epitaxial silicon layer. A larger interface area between N-doped and P-doped regions generally increases the capacitance. By providing the N-doped strip portions, as opposed to a continuous N-doped region, the combined interface area between the N-doped strip portions and the underlying epitaxial silicon layer is reduced. However, more interface area is provided between the N-doped strip portions and the P-doped strip portions. A circuit simulation indicates that junction capacitance per unit peripheral length is 0.41 fF/&#x3bc;m, while the junction capacitance per unit area is 0.19 fF/&#x3bc;m^2. Junction capacitance per unit peripheral length thus scales faster than junction capacitance per unit area.

Intrinsic decoupling capacitor

An apparatus is constituted with an integrated circuit and a flex tape coupled to the integrated circuit. The flex tape is employed to facilitate ingress/egress of signals to/from the integrated circuit. In one embodiment, the flex tape includes a plurality of signal traces. In another embodiment, the apparatus also includes a silicon interposer coupled to the flex tape and a substrate coupled to the silicon interposer.

Silicon building block architecture with flex tape

An embodiment of the present invention is a technique to integrate passive components in a die assembly. A capacitor, inductor, or resistor is integrated on a spacer between upper and lower dies in stacked dies. Conductors are attached to the capacitor, inductor or resistor to connect the capacitor, inductor, or resistor to at least one of the upper and lower dies.

Integrating passive components on spacer in stacked dies

A apparatus is disclosed for use as part of the packaging of an integrated circuit. The apparatus includes one or more flex tapes coupled to the integrated circuit. These flex tapes are utilized to deliver power to the integrated circuit.

Power delivery through a flex tape in decoupled I/O-power hybrid substrate

According to one aspect of the invention, a electronic assembly is provided. The electronic assembly includes a motherboard, a first microelectronic die on a package substrate, a second microelectronic die, and a strip of flex tape interconnecting the microelectronic dies. The package substrate has a metal core with via openings, power conductors connecting a top and bottom surface of the substrate and passing through the via openings, and ground conductors interconnecting the metal core with the top and bottom surface of the package substrate. The flex tape has signal conductors which interconnect the microelectronic dies. Power is provided to the first microelectronic die via the power conductors. IO signals are sent between the microelectronic dies over the signal conductors in the flex tape.

Electronic assembly

Leakage current may be reduced in trench isolated semiconductor devices by providing a buffer between the trench isolation and an active area. For example, with a trench isolated photodiode, a buffer of opposite conductivity type may be provided between the trench and the diffusion that forms the p-n junction of the photodiode.

Reduced leakage trench isolation

Leakage current may be reduced in trench isolated semiconductor devices by providing a buffer between the trench isolation and an active area For example, with a trench isolated photodiode, a buffer of opposite conductivity type may be provided between the trench and the diffusion that forms the p-n junction of the photodiode.

An embodiment of the invention is directed to a semiconductor photodiode made of a number of gate islands being spaced from each other and electrically insulated from each other by spacers. The spacers are formed above a p-n junction of the photodiode. The incident light is detected after it passes through the spacers and into a photosensitive region of the photodiode. The photodiode can be built using conventional metal oxide semiconductor (MOS) processes of the polysilicon-silicided gate or self-aligned types that use a lower doped drain (LDD) structure, without requiring an additional mask step that prevents the formation of the opaque silicide above the photosensitive semiconductor regions.

Photodiode having transparent insulating film around gate islands above P-N junction

The present invention is an image sensor and its fabricating method. The image sensor comprises a photodiode and a dielectric structure. The photodiode is responsive to an amount of incident light from a light source. The dielectric structure is on top of the photodiode and is placed between the photodiode and an inter-level dielectric (ILD) oxide layer. The dielectric structure contains a dielectric material. The ILD oxide layer is made of an oxide material and has an ILD oxide thickness.

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Chandler, AZ, United States of America

Jung S Kang