Hyundai Electronics Industries Co. Ltd.

Hynix Semiconductor Inc.

Jung Pill Kim

Joon Ho Kim

Jong Hoon Oh

In Chul Jung

Kee Woo Park

In one method according to an embodiment of the invention, a reference bitline is biased and a refresh period of a DRAM cell is increased. In one example of such a method, biasing the reference bitline includes applying a predetermined bias voltage. In a memory device according to one embodiment of the invention, a bias circuit includes a bias capacitor connected to a bitline and configured and arranged to receive a bias signal.

Increasing a refresh period in a semiconductor memory device

An antifuse stabilizing apparatus for a memory device stabilizes a programming process of an antifuse. A serial antifuse block has a plurality of antifuses being interconnected in series, and is programmed by applying a voltage being higher than an appropriate applying voltage of each antifuse. An antifuse programming block applies a program voltage being higher than the appropriate applying voltage to both ends of each antifuse in order to program the antifuses. A high voltage portion and a low voltage portion check a coupling state of the antifuses of the serial antifuse block. The applying voltage higher than the appropriate applying voltage is a voltage to be applied to both ends of each antifuse by the antifuse programming block. As a result, all circuits of using an antifuse whose appropriate applying voltage is lower than a power-supply voltage of the peripheral circuit can use the antifuse stably without using an additional circuit.

Apparatus for stabilizing an antifuse used for a memory device

A semiconductor device for automatically detecting an external interface voltage is disclosed, including a voltage converter for receiving an external interface voltage, and decreasing the external interface voltage value, and a voltage comparator for comparing the voltage outputted from the voltage converter with the internal supply voltage of a semiconductor chip. The semiconductor device automatically detects an external interface voltage environment where the semiconductor chip is used, and also automatically controls the magnitude of output buffer of the semiconductor chip according to the detected external interface voltage value, to prevent the operation speed from being deterioration.

Semiconductor device for automatically detecting external interface

An auto mode selector for a semiconductor memory device having a reference voltage selection switching circuit connected between a reference voltage pin and an internal reference voltage terminal, for selecting one of CTT and LVTTL in response to a reference voltage selection signal. The auto mode selector further includes an input leakage current controller for allowing current to flow through a resistor between a supply voltage source and the reference voltage pin only for a predetermined time period in response to an input leakage current control signal from an input leakage current control signal generator. According to the present invention, the amount of input leakage current and standby current can be reduced.

Auto mode selector

A fuse option circuit for memory device capable of performing the function of the fuse option circuit completely even in the case that the fuse is incompletely connected, is disclosed. The fuse option circuit according to the present invention includes a transistor serially connected to the fuse for alternatively selecting the turn-on resistance of the transistor being greater than the resistive components of the fuse when the fuse is stably connected, and smaller when the fuse is unstably disconnected, such that the advantageous effects which improve the production yield of the semiconductor device can be obtained by clearly determining the fuse connection state of the fuse option circuit.

Fuse option circuit for memory device

A synchronous memory device having a plurality of clock input buffers includes a first clock input buffer for generating an enable signal of a data output buffer, and a second clock input buffer for generating a signal to latch external input signals (i.e., an address signal, a row address strobe (RAS) signal, a column address strobe (CAS) signal and so on). As a result, the synchronous memory device achieves a clock access time of a high speed, and reduces a current consumption in a standby mode.

Synchronous memory device having a plurality of clock input buffers

A differential amplifier comprising a first NMOS transistor having its gate for receiving a first input signal, a second NMOS transistor having its gate for receiving a second input signal, a first PMOS transistor connected between the first NMOS transistor and a supply voltage source, a second PMOS transistor connected between the second NMOS transistor and the supply voltage source and having its gate connected to a gate of the first PMOS transistor through a first common node, and a current source circuit connected between a second common node of the first and second NMOS transistors and a ground voltage source, the current source circuit including a third NMOS transistor having its gate for receiving an enable signal and a fourth NMOS transistor connected in series to the third NMOS transistor and having its gate for receiving the first or second input signal. According to the present invention, current consumption amount is reduced in a standby mode where no input signal is applied.

Differential amplifier with reduced current consumption

An automatic mode selection circuit for automatically selecting low voltage transistor transistor logic and high-speed input/output interface modes in a semiconductor memory device. The automatic mode selection circuit comprises an external reference voltage pad for delivering an external reference voltage, an internal reference voltage generator for generating an internal reference voltage, a power-on detector for detecting a power-on time point and then generating a pulse signal for a predetermined time period, a switching circuit for switching the external reference voltage from the external reference voltage pad and the internal reference voltage from the internal reference voltage generator in response to an output signal from the power-on detector, a reference voltage detector connected between the external reference voltage pad and the switching circuit for detecting the external reference voltage from the external reference voltage pad, a comparator for comparing an output voltage from the reference voltage detector with the internal reference voltage from the internal reference voltage generator in response to the output signal from the power-on detector, and a latch circuit for latching an output signal from the comparator and supplying the latched signal to an output terminal.

Automatic mode selection circuit for semiconductor memory device

A method for driving word lines in a semiconductor memory device. A main row decoder generates a word line enable signal in s response to one part of address signal bits and a sub row decoder generates a word line boosting signal in response to the other part of the address signal bits. A bootstrap transistor transfers the word line enable signal from the main row decoder to a bootstrap node in response to a specific voltage. A high level voltage transfer transistor transfers the word line boosting signal from the sub row decoder to a corresponding one of the word lines in response to a voltage at the bootstrap node. After the word line enable signal from the main row decoder makes a low to high transition in level, the word line boosting signal from the sub row decoder is changed from a ground voltage level to a high voltage level to drive the corresponding word line. Then, the specific voltage is changed from the present level to the lower level. According to the present invention, the word line driving method can prevent a selected word line from floating due to OFF current resulting from a low level voltage at the bootstrap node when a row address strobe signal has a long duration. Furthermore, the word line driving method has the effect of enhancing the bootstrapping efficiency.

Method for driving word lines in semiconductor memory device

A sense amplifier for sensing and amplifying data existing at a pair of bit lines in a DRAM and having double power lines for supplying separate supply voltages to a P-channel sense amplifying unit and to an N-channel sense amplifying unit in a partially activatable DRAM and comprising a memory cell array apparatus having a pair of bit lines BL and BL is disclosed whereby a peak current occurrence in the partially activatable DRAM is prevented and the sensing ability of the sense amplifier is increased.

Growing community of inventors

Ichon-shi, South Korea

Jung Pill Kim