Samsung Electronics Co., Ltd.

Jung-Pil Lim

Hyunwook Lim

Kyungho Ryu

Yongil Kwon

Kilhoon Lee

Yong-Yun Park

Sunkwon Kim

Jinyong Park

Jae-Suk Yu

Jae-Youl Lee

Jaeyoul Lee

Dong-hoon Baek

Hyun-Wook Lim

Dong-Myung Lee

Sugyeung Kang

Jae-youl Lee

Kang Joo Kim

Han-su Pae

Alankyongho Kim

Hansu Pae

Junil Park

Alan Kyongho Kim

Kyung-Ho Ryu

Provided is a communication system including a first electronic device and a second electronic device connected with each other through first and second channels. The second electronic device includes a reception driver generating a first internal signal based on a first data signal provided by the first electronic device through the first channel, an error detector generating an error detection signal by determining whether an error is included in the first internal signal, and an error adjuster outputting a first feedback signal through the second channel based on the error detection signal, and the first electronic device outputs a second data signal having a voltage swing width determined based on the first feedback signal through the first channel.

Electronic device and communication system including the same

In a backlight apparatus, a master driving circuit generates a transmission frame including a training period including a clock training pattern and a data period including a plurality of data packets respectively corresponding to the plurality of blocks. A plurality of slave driving circuits correspond to the plurality of blocks, respectively, and are connected to the master driving circuit in a daisy chain structure. Each slave driving circuit receives the transmission frame through the daisy chain structure, recovers a clock based on the clock training pattern, and drives the plurality of light emitting elements included in a corresponding block among the plurality of blocks based on its own data packet among a plurality of data packets.

Backlight apparatus and operating method thereof

The present disclosure provides methods and apparatuses for correcting skew. In some embodiments, a skew correcting device includes a plurality of samplers configured to sample first data based on a plurality of data clock signals with different phases, and a plurality of edge selectors configured to determine to switch at least one data clock signal of the plurality of data clock signals to an edge clock signal according to a sampling result of the plurality of samplers.

Semiconductor device and operating method thereof

An electronic circuit includes a clock recovery circuit that generates a first reference clock signal based on first reception data and generates a second reference clock signal based on second reception data received after the first reception, a sampling clock generator that generates a sampling clock signal having a phase based on a phase difference between the first reference clock signal and the second reference clock signal, and a sampler that recovers the second reception data based on the generated sampling clock signal.

Electronic circuit configured to adjust sampling timing for recovering data

A method of recovering a clock and data from an input data signal including an embedded clock, the method including generating a recovery clock signal from the input data signal based on a first window signal; detecting a unit interval corresponding to one bit of the input data signal based on the recovery clock signal; delaying a signal synchronized with the recovery clock signal based on the unit interval; and generating the first window signal based on the delayed signal.

Clock data recovery circuit, apparatus including same and method for recovery clock and data

A clock and data recovery (CDR) circuit of a source driver includes a clock recovery unit and a delay locked loop unit. The clock recovery unit receives data bits and a clock code periodically inserted into the data bits through a clock embedded data channel in a display data mode, and is configured to generate a clock signal by detecting an edge of the clock code. The delay locked loop unit is configured to generate a multi-phase clock signal based on the clock signal in the display data mode.

Clock and data recovery circuit of a source driver and a display device

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Hwaseong-si, South Korea

Jung-Pil Lim