Samsung Electronics Co., Ltd.

Jung-Moo Lee

Hideki Horii

Dong-Ho Ahn

Seung-Jae Jung

Seong-Geon Park

Youn-Seon Kang

Jin-Woo Lee

Soon-Oh Park

Jong-Uk Kim

Jung-hwan Park

Hyun-Su Ju

Sug-woo Jung

Jung-dal Choi

Masayuki Terai

Dong-Jun Seong

Seol Young Choi

Min-kyu Yang

A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines.

Variable resistance memory device and method of manufacturing the same

A method of manufacturing a magnetoresistive random access memory device, the method including forming a memory structure on a substrate, the memory structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked; forming a first capping layer to cover a surface of the memory structure by a deposition process using a plasma under first conditions; and forming a second capping layer on the first capping layer by a deposition process using a plasma under second conditions different from the first conditions.

Magnetoresistive random access memory device

A variable resistance memory device may include: a first electrode layer; a selection device layer on the first electrode layer, the selection device layer including a chalcogenide switching material consisting essentially of germanium (Ge), selenium (Se), and antimony (Sb), wherein a content of the Ge is less than a content of the Se based on an atomic weight; a second electrode layer on the selection device layer; a variable resistance layer on the second electrode layer, the variable resistance layer including a chalcogenide material; and a third electrode layer on the variable resistance layer.

Magnetoresistive random access memory device and method of manufacturing the same

A semiconductor device includes a first electrode on a substrate, a selection device pattern, a variable resistance layer pattern, a first protective layer pattern, a second protective layer pattern and a second electrode. The selection device pattern is wider, in a given direction, than the variable resistance layer pattern. The first protective layer pattern is formed on a first pair of opposite sides of the variable resistance layer pattern. The second protective layer pattern is formed on a second pair of opposite of the variable resistance layer pattern. The second electrode is disposed on the variable resistance layer pattern.

Semiconductor devices and methods of manufacturing the same

A variable resistance memory device includes a plurality of first conductive lines, a plurality of second conductive lines, a plurality of memory cells, a plurality of first air gaps and a plurality of second air gaps. The first conductive line extends in a first direction. The second conductive line is over the first conductive line and extends in a second direction crossing the first direction. The memory cell includes a variable resistance device. The memory cell is located at an intersection region of the first conductive line and the second conductive line. The first air gap extends in the first direction between the memory cells. The second air gap extends in the second direction between the memory cells.

Variable resistance memory devices

A memory device is provided. The memory device includes bit lines that extend in a first direction on a substrate, word lines configured to vertically cross the bit lines, memory cells formed at intersections of the bit lines and the word lines, a first low permittivity layer configured to fill spaces between the bit lines and partially fill spaces between the memory cells formed on bottom surfaces of the word lines, a first dielectric layer stacked on an upper surface of the first low permittivity layer between the memory cells, a second dielectric layer configured to fill spaces between the memory cells formed on upper surfaces of the bit lines, and a second low permittivity layer stacked on an upper surface of the second dielectric layer and configured to fill spaces between the word lines. The first and second low permittivity layers have lower permittivity than the first and second dielectric layers.

Memory devices having low permittivity layers and methods of fabricating the same

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Hwaseong-si, South Korea

Jung-Moo Lee