Intel Corporation

Tahoe Research, Ltd.

Jung Kyu Han

Srinivas V Pietambaram

Steve S Cho

Ali Lehaf

Kristof Darmawikarta

Robert Alan May

Sri Ranga Sai Boyapati

Hiroki Tanaka

Thomas Heaton

Rahul N Manepalli

Xiaoying Guo

Hongxia Feng

Gang Duan

Dingying David Xu

Sashi S Kandanur

Aleksandar Aleksov

Leonel R Arana

Dilan Seneviratne

Bai Nie

Haobo Chen

Ravindranadh T Eluri

Kyle Mcelhinny

Yue Deng

Kristof Darmawaikarta

Yonggang Li

Jeremy D Ecton

Chong Zhang

Amram Eitan

Changhua Liu

Kyle Jordan Arrington

Meizi Jiao

Yosuke Kanaoka

Matthew L Tingey

Sameer Paital

Jesse Jones

Srinivas Venkata Ramanuja Pietambaram

Bohan Shan

Wei Wei

Onur Ozkan

Liang He

Alexander Aguinaga

Santosh Tripathi

A computer apparatus includes a hierarchy of solder joints in a multi-chip package, with solder joints at different levels of the packaging having different melting temperatures. Interconnections, such as pads or pins, on integrated circuit (IC) die can be electrically coupled to ends of contact pillars with solder joints having a higher melting temperature. The other ends of the contact pillars can electrically couple to another substrate or another device with solder joints having a lower melting temperature. The contact pillars can be, for example, a contact array or through-hole via in a substrate.

Solder interconnect hierarchy for heterogeneous electronic device packaging

Various embodiments disclosed relate to methods of making omni-directional semiconductor interconnect bridges. The present disclosure includes semiconductor assemblies including a mold layer having mold material, a first filler material dispersed in the mold material, and a second filler material dispersed in the mold material, wherein the second filler material is heterogeneously dispersed.

Omni directional interconnect with magnetic fillers in mold matrix

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes bumps to electrically couple the die to the substrate. Ones of the bumps have corresponding bases. The bases have a shape that is non-circular.

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes an array of bumps to electrically couple the die to the substrate. Each of the bumps have a corresponding base. Different ones of the bases have different widths that vary spatially across the array of bumps.

Methods and apparatus to reduce defects in interconnects between semicondcutor dies and package substrates

Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate and a bridge substrate embedded in the package substrate. In an embodiment, first pads are over the package substrate, where the first pads have a first pitch, and second pads are over the bridge substrate, where the second pads have a second pitch that is smaller than the first pitch. In an embodiment, a barrier layer is over individual ones of the second pads. In an embodiment, reflown solder is over individual ones of the first pads and over individual ones of the second pads. In an embodiment, a first standoff height of the reflown solder over the first pads is equal to a second standoff height of the reflown solder over the second pads.

Architecture to manage FLI bump height delta and reliability needs for mixed EMIB pitches

Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

Surface finishes with low RBTV for fine and mixed bump pitch architectures

A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

Patternable die attach materials and processes for patterning

A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.

Electromigration resistant and profile consistent contact arrays

Surface finishes with low rBTV for fine and mixed bump pitch architectures

Growing community of inventors

Chandler, AZ, United States of America

Jung Kyu Han