Samsung Electronics Co., Ltd.

Jung-Joon Lee

Byung-Se So

Jeong-Hyeon Cho

Sung-joo Park

Kyoung-Sun Kim

Jea-Eun Lee

Do-Hyung Kim

Jae-jun Lee

Bok-moon Kang

Kwang-Soo Park

Young Nam Yun

Jae-Jun Lee

Yang-Ki Kim

Byung-se So

Young-Jun Park

You-Keun Han

Seung-Jin Seo

Seok-Il Kim

Ki-Hyun Ko

Beom-Sig Cho

Kwang-Seop Kim

Chil-Nam Yoon

Jong-ryeul Kim

Sung-Joo Park

Chang-Woo Koo

Baek Kyu Choi

Il-Sung Yu

A semiconductor module assembly is provided. The semiconductor module assembly includes a motherboard, a socket, and a semiconductor module. The motherboard includes an opening for receiving the semiconductor module, the opening including at least three sides. The socket is disposed in the opening along at least a first side, second side, and third side of the at least three sides. The semiconductor module is disposed in the socket. The semiconductor module includes at least one semiconductor device mounted on a module board. The socket includes at least a first side along the first side of the opening, and a second side along the second side of the opening, and the semiconductor module electrically connects to the motherboard through at least the first and second sides of the socket.

Semiconductor module assembly

A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path. The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal.

Data receiver, semiconductor device and memory device including the same

A memory module comprises a plurality of semiconductor memory devices each having a termination circuit for a command/address bus. The semiconductor memory devices are formed in a substrate of the memory module, and they operate in response to a command/address signal, a data signal, and a termination resistance control signal.

Memory module and memory system comprising memory module

A memory system includes an error detection circuit having an error counter. When a bit error rate (BER) determined by the error counter exceeds a reference BER, the memory system reduces the BER by adjusting its operating speed or operating voltage, re-performing data training or impedance matching, or by adjusting a data swing width. Accordingly, a method of controlling a bit error rate may be performed, and a system hang is prevented.

Memory system and method for preventing system hang

Pairs of registers with reduced pins are disposed to overlap on front and back surfaces of a memory module. An input signal INS is transferred through the registers in series in a daisy chain fashion to avoid divergence of the input signal INS for preserved signal integrity. Each register buffers the input signal INS to memory banks disposed closely to sides of the register for reduced wiring area.

Memory module with registers

A method of forming an integrated circuit module may include interposing an auxiliary PCB between at least one semiconductor chip and a main PCB, the auxiliary PCB having at least one circuit pattern for electrical connection to one of the semiconductor chip and at least one circuit pattern formed on the main PCB.

Integrated circuit module and method of forming the same

A semiconductor memory device includes an input data delay time adjustor for varying an input delay time, selecting one bit of a n-bit input data, delaying the selected one bit by the input delay time and outputting the delayed bit, in response to a control signal during an input data delay test operation; and an output data delay time adjustor for varying an output delay time, selecting one bit of a m-bit output data, delaying the selected one bit by the output delay time and outputting the delayed bit, in response to the control signal during an output data delay test operation, wherein the input data delay time adjustor is arranged for n-bit input data, and wherein the output data delay time adjustor is arranged for m-bit output data.

Semiconductor memory device and memory system using same

A memory module socket disposed on a principal surface of a mainboard, and adapted to mechanically receive and electrically connect a memory module with a mainboard, the memory module socket including a first unit socket having a plurality of first socket pins adapted to electrically connect a first connector disposed on an edge of the memory module, and a second unit socket having a plurality of second socket pins adapted to electrically connect to a second connector disposed on the memory module orthogonal to the first connector, wherein the memory module as installed in the memory module socket is parallel to the principal surface of the mainboard.

Memory module, memory module socket and mainboard using same

A memory module and a method of mounting memory devices on a PCB to form the memory module substantially reduce unnecessary routing space and improve signal attenuation characteristics. In the method of mounting and sequentially connecting at least two memory devices on a printed circuit board (PCB) having an axis of elongation to form a memory module, at least one of the memory devices is mounted on at least one face of the PCB so that a base line along an longitudinal axis of the at least one memory device lies at an acute angle with respect to the axis of elongation of the PCB.

Method of mounting memory device on PCB for memory module

Embodiments of the invention include a stacked board-on-chip (BOC) package having a mirroring structure and a dual inline memory module (DIMM) on which the stacked BOC package is mounted. A bottom surface of a first semiconductor chip faces a bottom surface of a second semiconductor chip. An interposer electrically connects first and second packages, respectively comprising the first and second semiconductor chips, to each other. The DIMM is obtained by electrically connecting BOC packages to each other on upper and lower substrates of a printed circuit board. Since a height of the stacked BOC packages is greater than a height of a conventional stacked BOC package, the DIMM has a minimum stub length and an optimal topology. Hence, the DIMM can have a signal with excellent fidelity by reducing a load upon a signal line, and installation or wiring of components within the DIMM 300 requires less effort.

Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip packages are mounted

A memory device includes a first termination unit coupled to a first pin for receiving a first signal having a first frequency component. The memory device also includes a second termination unit coupled to a second pin for receiving a second signal having a second frequency component higher than the first frequency component. The first termination unit is a different type from the second termination unit that provides less signal distortion than the first termination unit. For example, the first termination unit is of an open-drain type that has less power consumption, and the second termination unit is of a push-pull type that has less signal distortion.

Memory device with different termination units for different signal frequencies

The present invention discloses a memory module and a method of arranging a signal line of the same. The method of arranging a signal line of a memory module comprises: classifying a plurality of memories into a first group including an odd number of memories and a second group including an even number of memories; arranging first branch points corresponding to the plurality of memories and respectively connecting the first branch points to the plurality of memories through first signal lines; arranging a second branch point located at a middle of the second group for respectively connecting between the first branch points adjacent to each other of the second group and between the first branch points adjacent to the second branch points and the second branch point through second signal lines; arranging a third branch point located at a middle of the second group, receiving an external signal, and connecting the third branch point and the second branch point of the second group through a third signal line; and connecting between the second branch point of the second group and the first branch point of the first group through a fourth signal line.

Memory module and a method of arranging a signal line of the same

In the memory module, a buffer is disposed on one of at least two circuit boards in the memory module. The buffer is for buffering signals for memory chips on at least two circuit boards in the memory module.

Memory module

A ball grid array (BGA) package test module includes BGA packages, a module board, and test architecture for use in testing the BGA packages while they are mounted to the module board. The test architecture of the BGA package test module includes package test signal lines connected to solder balls of the BGA packages as extending along a bottom surface of the BGA packages, board test signal lines extending along the module board, and electrical junctions that interconnect the package and board test signal lines. Signals from the BGA packages can be picked up by the probe of a testing apparatus via the board test signal lines. The present invention is advantageous in that it minimizes the effect of stubbing by the test signal lines when the memory module is operating.

Module having test architecture for facilitating the testing of ball grid array packages, and test method using the same

A memory module and a method of packaging memory devices are provided. The method prepares semiconductor packages of the memory devices, each of which has external pins that include data pins and command signal pins, and mounts the packages on a printed circuit board, on which a first bus, a second bus, and a third bus are formed. The data pins of odd-numbered packages and even-numbered packages connect to the first bus and the second bus, respectively. The control signal pins connect to the third bus. Each package can optionally include dummy pins, where the dummy pins of the even-numbered packages and the odd-numbered packages respectively connect to the first and second buses so that each of the first, second and third buses connects to the same number of external pins. The pin assignment of the even-numbered packages can be different from the pin assignment of the odd-numbered packages to facilitate connections of the buses.

Growing community of inventors

Seoul, South Korea

Jung-Joon Lee