Samsung Electronics Co., Ltd.

Jung-In Kim

Jae-Hee Oh

Ji-Hyun Jeong

Sung-Ho Eun

Hyunho Kim

Yong-Won Shin

Yong-tae Oh

Jae-Hyun Park

Youngnam Hwang

Byoungjae Bae

Kiseok Suh

Seung-Pil Ko

Jun-hyok Kong

Joon-sang Ryu

Tae-Kyun Jung

Jaehee Oh

A neuromorphic processor may include at least a first synapse element. The first synapse element may include a first bit cell and a second bit cell, the first bit cell connected to a first bitline, a first inverted bitline, a first wordline, and a first inverted wordline, and the second bit cell connected to the first bitline, the first inverted bitline, a second wordline, and a second inverted wordline. The first synapse element may be configured to receive a first input through the first wordline, the first inverted wordline, the second wordline, and the second inverted wordline, store a first synapse value in the first bit cell and the second bit cell, perform a calculation operation using the first input and the first synapse value, and output a result of the calculation through the first bitline and the first inverted bitline.

Synapse element increasing a dynamic range of an output while suppressing and/or decreasing power consumption, and a neuromorphic processor including the synapse element

A method and apparatus for suppressing vocoder noise are provided. In the method, first information and second information are received from a channel decoder, the first information indicating whether a decoded data frame has an error and the second information being a channel quality metric, error concealment voice decoding is performed on the decoded data frame if the first information indicates that no channel decoding error has been generated and the second information is smaller than a predetermined first threshold, and normal voice decoding is performed on the decoded data frame if the first information indicates that no channel decoding error has been generated and the second information is equal to or larger than the first threshold.

Method and apparatus of suppressing vocoder noise

A method and an apparatus for reducing noise due to a path change of an audio signal output from a device are provided. The method includes determining an input period for canceling the noise by using a time point, at which the path change is sensed, as a reference, when sensing the path change of the audio signal; low-pass filtering the audio signal in the determined input period; and interpolating a first partial signal, which is the low-pass filtered audio signal in a first predetermined period that starts from a start time point of the determined input period, and a second partial signal, which is the low-pass filtered audio signal in a second predetermined period that ends at an end time point of the determined input period, within the determined input period.

Method and apparatus for reducing noise due to path change of audio signal

Provided are semiconductor devices and methods of fabricating the same. The device may include lower interconnection lines, upper interconnection lines crossing the lower interconnection lines, selection elements disposed at intersections, respectively, of the lower and upper interconnection lines, and memory elements interposed between the selection elements and the upper interconnection lines, respectively. Each of the selection elements may be realized using a semiconductor pattern having a first sidewall, in which a first lower width is smaller than a first upper width, and a second sidewall, in which a second lower width is greater than a second upper width, the first and second sidewalls crossing each other.

Semiconductor device and method of fabricating the same

Semiconductor memory devices having strapping contacts are provided, the devices include cell regions and strapping regions between adjacent cell regions in a first direction. Active patterns, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines, extending in the second direction, intersect the active patterns and first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions. The active patterns contact the first interconnection lines through strapping contacts in the strapping regions.

Semiconductor memory devices having strapping contacts

A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer.

Method of forming memory device

In a variable resistance memory device and a method of manufacturing the variable resistance memory device, the generation of a seam, or void, is avoided in the device that, if present, may otherwise reduce the reliability of the resulting device.

Variable resistance memory device and method of manufacturing the same

A method of forming a pattern structure and a method of fabricating a semiconductor device using the pattern structure, are provided the method of forming the pattern structure includes forming a mask on an underlying layer formed on a lower layer. The underlying layer is etched using the mask as an etching mask, thereby forming patterns on the lower layer. The patterns define at least one opening. A sacrificial layer is formed in the opening and the mask is removed. The sacrificial layer in the opening is partially etched when the mask is removed.

Method of forming pattern structure and method of fabricating semiconductor device using the same

A method of fabricating a semiconductor device includes forming a conductive layer on a semiconductor substrate, forming an insulating layer on the conductive layer, forming a word line and isolation trenches by patterning the insulating layer and the conductive layer, forming an isolation layer that fills the isolation trenches, forming a cell contact hole in the insulating layer such that the cell contact hole is self-aligned with the word line and exposes the word line, and forming a cell diode in the cell contact hole.

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Seoul, South Korea

Jung-In Kim